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clk: qcom: Add enable/disable to clk_regmap_mux_div_ops

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Add support for and enable and disable ops for regmap_mux_div clk, also
support for safe source for regmap_mux_div clock to park the clk to safe
source while disabling and restore to active rate when clk is enabled.

Change-Id: Ida765ec1853c2bdd17b6fce3e8012e294f4324fe
Signed-off-by: Naveen Yadav <naveenky@codeaurora.org>
This commit is contained in:
Naveen Yadav 2020-09-18 20:19:20 +05:30
parent 0e13e74f0c
commit c7546e1c9d
2 changed files with 31 additions and 0 deletions
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16
drivers/clk/qcom/clk-regmap-mux-div.c
View File

@ -228,7 +228,23 @@ static unsigned long mux_div_recalc_rate(struct clk_hw *hw, unsigned long prate)
return 0;
}
static int mux_div_enable(struct clk_hw *hw)
{
struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
return mux_div_set_src_div(md, md->src, md->div);
}
static void mux_div_disable(struct clk_hw *hw)
{
struct clk_regmap_mux_div *md = to_clk_regmap_mux_div(hw);
mux_div_set_src_div(md, md->safe_src, md->safe_div);
}
const struct clk_ops clk_regmap_mux_div_ops = {
.enable = mux_div_enable,
.disable = mux_div_disable,
.get_parent = mux_div_get_parent,
.set_parent = mux_div_set_parent,
.set_rate = mux_div_set_rate,

15
drivers/clk/qcom/clk-regmap-mux-div.h
View File

@ -19,6 +19,18 @@
* @src_shift: lowest bit of source select field
* @div: the divider raw configuration value
* @src: the mux index which will be used if the clock is enabled
* @safe_src: the safe source mux value we switch to, while the main PLL is
* reconfigured
* @safe_div: the safe divider value that we set, while the main PLL is
* reconfigured
* @safe_freq: When switching rates from A to B, the mux div clock will
* instead switch from A -> safe_freq -> B. This allows the
* mux_div clock to change rates while enabled, even if this
* behavior is not supported by the parent clocks.
* If changing the rate of parent A also causes the rate of
* parent B to change, then safe_freq must be defined.
* safe_freq is expected to have a source clock which is always
* on and runs at only one rate.
* @parent_map: pointer to parent_map struct
* @clkr: handle between common and hardware-specific interfaces
* @pclk: the input PLL clock
@ -32,6 +44,9 @@ struct clk_regmap_mux_div {
u32 src_shift;
u32 div;
u32 src;
u32 safe_src;
u32 safe_div;
unsigned long safe_freq;
const struct parent_map *parent_map;
struct clk_regmap clkr;
struct clk *pclk;