driver: thermal: msm_lmh_dcvs: Add a snapshot of LMH DCVS driver
Add a snapshot of LMH DCVS driver from msm-4.9 to msm-5.4 as of 'commit <162e59ac03498efd8b4cb6f0d162383cdf7ee140> (drivers: lmh_dcvs: Add support to selectively register cooling devices)' Remove the virtual sensor registration, LMH cooling device registration and LMH debug features, which are deprecated. Change-Id: Ia007db7b02e4965f4af48f0076f29ad1a0aeb0c1 Signed-off-by: Ram Chandrasekar <rkumbako@codeaurora.org>
This commit is contained in:
Ram Chandrasekar
parent
9e2415b0ae
commit
ca8f54030f
@ -80,3 +80,14 @@ config QTI_CPU_ISOLATE_COOLING_DEVICE
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scheduled and hence will let the CPU to power collapse. Isolating
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a CPU will be used when the CPU frequency mitigation
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is not good enough to achieve the necessary cooling.
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config QTI_THERMAL_LIMITS_DCVS
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tristate "QTI LMH DCVS Driver"
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depends on THERMAL_OF && QTI_THERMAL && CPU_THERMAL
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help
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This enables the driver for Limits Management Hardware - DCVS block
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for the application processors. The h/w block that is available for
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each cluster can be used to perform quick thermal mitigations by
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tracking temperatures of the CPUs and taking thermal action in the
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hardware without s/w intervention.
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@ -15,3 +15,4 @@ qti_qmi_cdev-y += thermal_mitigation_device_service_v01.o qmi_cooling.o
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obj-$(CONFIG_QTI_CPU_ISOLATE_COOLING_DEVICE) += cpu_isolate.o
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obj-$(CONFIG_QTI_BCL_PMIC5) += bcl_pmic5.o
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obj-$(CONFIG_QTI_BCL_SOC_DRIVER) += bcl_soc.o
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obj-$(CONFIG_QTI_THERMAL_LIMITS_DCVS) += msm_lmh_dcvs.o
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421
drivers/thermal/qcom/msm_lmh_dcvs.c
Normal file
421
drivers/thermal/qcom/msm_lmh_dcvs.c
Normal file
@ -0,0 +1,421 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2016-2020, The Linux Foundation. All rights reserved.
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*/
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#define pr_fmt(fmt) "%s:%s " fmt, KBUILD_MODNAME, __func__
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#include <linux/module.h>
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#include <linux/slab.h>
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#include <linux/thermal.h>
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#include <linux/of.h>
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#include <linux/of_device.h>
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#include <linux/of_irq.h>
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#include <linux/of_address.h>
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#include <linux/platform_device.h>
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#include <linux/sched.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/timer.h>
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#include <linux/pm_opp.h>
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#include <linux/atomic.h>
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#include <linux/regulator/consumer.h>
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#include <asm/smp_plat.h>
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#include <asm/cacheflush.h>
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#include "../thermal_core.h"
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#define LIMITS_DCVSH 0x10
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#define LIMITS_NODE_DCVS 0x44435653
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#define LIMITS_SUB_FN_THERMAL 0x54484D4C
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#define LIMITS_HI_THRESHOLD 0x48494748
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#define LIMITS_LOW_THRESHOLD 0x4C4F5700
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#define LIMITS_ARM_THRESHOLD 0x41524D00
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#define LIMITS_CLUSTER_0 0x6370302D
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#define LIMITS_CLUSTER_1 0x6370312D
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#define LIMITS_FREQ_CAP 0x46434150
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#define LIMITS_TEMP_DEFAULT 75000
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#define LIMITS_TEMP_HIGH_THRESH_MAX 120000
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#define LIMITS_LOW_THRESHOLD_OFFSET 500
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#define LIMITS_POLLING_DELAY_MS 10
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#define LIMITS_CLUSTER_REQ_OFFSET 0x704
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#define LIMITS_CLUSTER_INT_CLR_OFFSET 0x8
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#define dcvsh_get_frequency(_val, _max) do { \
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_max = (_val) & 0x3FF; \
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_max *= 19200; \
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} while (0)
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#define FREQ_KHZ_TO_HZ(_val) ((_val) * 1000)
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#define FREQ_HZ_TO_KHZ(_val) ((_val) / 1000)
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enum lmh_hw_trips {
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LIMITS_TRIP_ARM,
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LIMITS_TRIP_HI,
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LIMITS_TRIP_MAX,
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};
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struct __limits_cdev_data {
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struct thermal_cooling_device *cdev;
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u32 max_freq;
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};
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struct limits_dcvs_hw {
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char sensor_name[THERMAL_NAME_LENGTH];
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uint32_t affinity;
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int irq_num;
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void *osm_hw_reg;
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void *int_clr_reg;
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cpumask_t core_map;
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struct delayed_work freq_poll_work;
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unsigned long max_freq[NR_CPUS];
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unsigned long hw_freq_limit;
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struct device_attribute lmh_freq_attr;
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struct list_head list;
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bool is_irq_enabled;
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struct mutex access_lock;
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struct __limits_cdev_data *cdev_data;
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uint32_t cdev_registered;
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struct regulator *isens_reg[2];
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};
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LIST_HEAD(lmh_dcvs_hw_list);
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DEFINE_MUTEX(lmh_dcvs_list_access);
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static void limits_dcvs_get_freq_limits(struct limits_dcvs_hw *hw)
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{
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unsigned long freq_ceil = UINT_MAX, freq_floor = 0;
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struct device *cpu_dev = NULL;
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uint32_t cpu, idx = 0;
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for_each_cpu(cpu, &hw->core_map) {
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freq_ceil = UINT_MAX;
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freq_floor = 0;
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cpu_dev = get_cpu_device(cpu);
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if (!cpu_dev) {
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pr_err("Error in get CPU%d device\n", cpu);
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idx++;
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continue;
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}
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dev_pm_opp_find_freq_floor(cpu_dev, &freq_ceil);
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dev_pm_opp_find_freq_ceil(cpu_dev, &freq_floor);
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hw->max_freq[idx] = freq_ceil / 1000;
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idx++;
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}
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}
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static unsigned long limits_mitigation_notify(struct limits_dcvs_hw *hw)
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{
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uint32_t val = 0, max_cpu_ct = 0, max_cpu_limit = 0, idx = 0, cpu = 0;
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struct device *cpu_dev = NULL;
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unsigned long freq_val, max_limit = 0;
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struct dev_pm_opp *opp_entry;
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val = readl_relaxed(hw->osm_hw_reg);
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dcvsh_get_frequency(val, max_limit);
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for_each_cpu(cpu, &hw->core_map) {
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cpu_dev = get_cpu_device(cpu);
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if (!cpu_dev) {
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pr_err("Error in get CPU%d device\n",
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cpumask_first(&hw->core_map));
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goto notify_exit;
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}
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pr_debug("CPU:%d max value read:%lu\n",
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cpumask_first(&hw->core_map),
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max_limit);
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freq_val = FREQ_KHZ_TO_HZ(max_limit);
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opp_entry = dev_pm_opp_find_freq_floor(cpu_dev, &freq_val);
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/*
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* Hardware mitigation frequency can be lower than the lowest
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* possible CPU frequency. In that case freq floor call will
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* fail with -ERANGE and we need to match to the lowest
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* frequency using freq_ceil.
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*/
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if (IS_ERR(opp_entry) && PTR_ERR(opp_entry) == -ERANGE) {
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opp_entry = dev_pm_opp_find_freq_ceil(cpu_dev,
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&freq_val);
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if (IS_ERR(opp_entry))
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dev_err(cpu_dev,
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"frequency:%lu. opp error:%ld\n",
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freq_val, PTR_ERR(opp_entry));
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}
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if (FREQ_HZ_TO_KHZ(freq_val) == hw->max_freq[idx]) {
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max_cpu_ct++;
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if (max_cpu_limit < hw->max_freq[idx])
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max_cpu_limit = hw->max_freq[idx];
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idx++;
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continue;
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}
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max_limit = FREQ_HZ_TO_KHZ(freq_val);
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break;
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}
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if (max_cpu_ct == cpumask_weight(&hw->core_map))
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max_limit = max_cpu_limit;
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sched_update_cpu_freq_min_max(&hw->core_map, 0, max_limit);
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pr_debug("CPU:%d max limit:%lu\n", cpumask_first(&hw->core_map),
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max_limit);
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notify_exit:
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hw->hw_freq_limit = max_limit;
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return max_limit;
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}
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static void limits_dcvs_poll(struct work_struct *work)
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{
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unsigned long max_limit = 0;
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struct limits_dcvs_hw *hw = container_of(work,
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struct limits_dcvs_hw,
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freq_poll_work.work);
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int cpu_ct = 0, cpu = 0, idx = 0;
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mutex_lock(&hw->access_lock);
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if (hw->max_freq[0] == U32_MAX)
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limits_dcvs_get_freq_limits(hw);
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max_limit = limits_mitigation_notify(hw);
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for_each_cpu(cpu, &hw->core_map) {
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if (max_limit >= hw->max_freq[idx])
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cpu_ct++;
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idx++;
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}
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if (cpu_ct >= cpumask_weight(&hw->core_map)) {
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writel_relaxed(0xFF, hw->int_clr_reg);
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hw->is_irq_enabled = true;
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enable_irq(hw->irq_num);
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} else {
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mod_delayed_work(system_highpri_wq, &hw->freq_poll_work,
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msecs_to_jiffies(LIMITS_POLLING_DELAY_MS));
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}
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mutex_unlock(&hw->access_lock);
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}
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static void lmh_dcvs_notify(struct limits_dcvs_hw *hw)
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{
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if (hw->is_irq_enabled) {
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hw->is_irq_enabled = false;
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disable_irq_nosync(hw->irq_num);
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limits_mitigation_notify(hw);
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mod_delayed_work(system_highpri_wq, &hw->freq_poll_work,
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msecs_to_jiffies(LIMITS_POLLING_DELAY_MS));
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}
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}
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static irqreturn_t lmh_dcvs_handle_isr(int irq, void *data)
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{
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struct limits_dcvs_hw *hw = data;
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mutex_lock(&hw->access_lock);
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lmh_dcvs_notify(hw);
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mutex_unlock(&hw->access_lock);
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return IRQ_HANDLED;
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}
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static void limits_isens_qref_init(struct platform_device *pdev,
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struct limits_dcvs_hw *hw,
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int idx, char *reg_name,
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char *reg_setting)
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{
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int ret = 0;
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uint32_t settings[3];
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ret = of_property_read_u32_array(pdev->dev.of_node,
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reg_setting, settings, 3);
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if (ret) {
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if (ret == -EINVAL)
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return;
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pr_err("Regulator:isens_vref settings read error:%d\n",
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ret);
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return;
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}
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hw->isens_reg[idx] = devm_regulator_get(&pdev->dev, reg_name);
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if (IS_ERR_OR_NULL(hw->isens_reg[idx])) {
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pr_err("Regulator:isens_vref init error:%ld\n",
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PTR_ERR(hw->isens_reg[idx]));
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return;
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}
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ret = regulator_set_voltage(hw->isens_reg[idx], settings[0],
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settings[1]);
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if (ret) {
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pr_err("Regulator:isens_vref set voltage error:%d\n", ret);
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return;
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}
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ret = regulator_set_load(hw->isens_reg[idx], settings[2]);
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if (ret) {
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pr_err("Regulator:isens_vref set load error:%d\n", ret);
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return;
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}
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if (regulator_enable(hw->isens_reg[idx])) {
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pr_err("Failed to enable regulator:isens_vref\n");
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return;
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}
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}
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static void limits_isens_vref_ldo_init(struct platform_device *pdev,
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struct limits_dcvs_hw *hw)
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{
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limits_isens_qref_init(pdev, hw, 0, "isens_vref_1p8",
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"isens-vref-1p8-settings");
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limits_isens_qref_init(pdev, hw, 1, "isens_vref_0p8",
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"isens-vref-0p8-settings");
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}
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static ssize_t
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lmh_freq_limit_show(struct device *dev, struct device_attribute *devattr,
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char *buf)
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{
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struct limits_dcvs_hw *hw = container_of(devattr,
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struct limits_dcvs_hw,
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lmh_freq_attr);
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return scnprintf(buf, PAGE_SIZE, "%lu\n", hw->hw_freq_limit);
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}
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static int limits_dcvs_probe(struct platform_device *pdev)
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{
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int ret;
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int affinity = -1;
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struct limits_dcvs_hw *hw;
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struct device_node *dn = pdev->dev.of_node;
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struct device_node *cpu_node, *lmh_node;
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uint32_t request_reg, clear_reg;
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int cpu, idx = 0;
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cpumask_t mask = { CPU_BITS_NONE };
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const __be32 *addr;
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for_each_possible_cpu(cpu) {
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cpu_node = of_cpu_device_node_get(cpu);
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if (!cpu_node)
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continue;
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lmh_node = of_parse_phandle(cpu_node, "qcom,lmh-dcvs", 0);
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if (lmh_node == dn) {
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/*set the cpumask*/
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cpumask_set_cpu(cpu, &(mask));
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}
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of_node_put(cpu_node);
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of_node_put(lmh_node);
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}
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hw = devm_kzalloc(&pdev->dev, sizeof(*hw), GFP_KERNEL);
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if (!hw)
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return -ENOMEM;
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/*
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* We just init regulator if none of the CPUs have
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* reference to our LMH node
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*/
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if (cpumask_empty(&mask)) {
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limits_isens_vref_ldo_init(pdev, hw);
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mutex_lock(&lmh_dcvs_list_access);
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INIT_LIST_HEAD(&hw->list);
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list_add_tail(&hw->list, &lmh_dcvs_hw_list);
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mutex_unlock(&lmh_dcvs_list_access);
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return 0;
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}
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hw->cdev_data = devm_kcalloc(&pdev->dev, cpumask_weight(&mask),
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sizeof(*hw->cdev_data),
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GFP_KERNEL);
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if (!hw->cdev_data)
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return -ENOMEM;
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cpumask_copy(&hw->core_map, &mask);
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hw->cdev_registered = 0;
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for_each_cpu(cpu, &hw->core_map) {
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hw->cdev_data[idx].cdev = NULL;
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hw->cdev_data[idx].max_freq = U32_MAX;
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hw->max_freq[idx] = U32_MAX;
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idx++;
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}
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ret = of_property_read_u32(dn, "qcom,affinity", &affinity);
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if (ret)
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return -ENODEV;
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switch (affinity) {
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case 0:
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hw->affinity = LIMITS_CLUSTER_0;
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break;
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case 1:
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hw->affinity = LIMITS_CLUSTER_1;
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break;
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default:
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return -EINVAL;
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}
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addr = of_get_address(dn, 0, NULL, NULL);
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if (!addr) {
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pr_err("Property llm-base-addr not found\n");
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return -EINVAL;
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}
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clear_reg = be32_to_cpu(addr[0]) + LIMITS_CLUSTER_INT_CLR_OFFSET;
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addr = of_get_address(dn, 1, NULL, NULL);
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if (!addr) {
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pr_err("Property osm-base-addr not found\n");
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return -EINVAL;
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}
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request_reg = be32_to_cpu(addr[0]) + LIMITS_CLUSTER_REQ_OFFSET;
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hw->hw_freq_limit = U32_MAX;
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snprintf(hw->sensor_name, sizeof(hw->sensor_name), "limits_sensor-%02d",
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affinity);
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mutex_init(&hw->access_lock);
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INIT_DEFERRABLE_WORK(&hw->freq_poll_work, limits_dcvs_poll);
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hw->osm_hw_reg = devm_ioremap(&pdev->dev, request_reg, 0x4);
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if (!hw->osm_hw_reg) {
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pr_err("register remap failed\n");
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goto probe_exit;
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}
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hw->int_clr_reg = devm_ioremap(&pdev->dev, clear_reg, 0x4);
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if (!hw->int_clr_reg) {
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pr_err("interrupt clear reg remap failed\n");
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goto probe_exit;
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}
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hw->irq_num = of_irq_get(pdev->dev.of_node, 0);
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if (hw->irq_num < 0) {
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pr_err("Error getting IRQ number. err:%d\n", hw->irq_num);
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goto probe_exit;
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}
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hw->is_irq_enabled = true;
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ret = devm_request_threaded_irq(&pdev->dev, hw->irq_num, NULL,
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lmh_dcvs_handle_isr, IRQF_TRIGGER_HIGH | IRQF_ONESHOT
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| IRQF_NO_SUSPEND | IRQF_SHARED, hw->sensor_name, hw);
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if (ret) {
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pr_err("Error registering for irq. err:%d\n", ret);
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ret = 0;
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goto probe_exit;
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}
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limits_isens_vref_ldo_init(pdev, hw);
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hw->lmh_freq_attr.attr.name = "lmh_freq_limit";
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hw->lmh_freq_attr.show = lmh_freq_limit_show;
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hw->lmh_freq_attr.attr.mode = 0444;
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device_create_file(&pdev->dev, &hw->lmh_freq_attr);
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probe_exit:
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mutex_lock(&lmh_dcvs_list_access);
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INIT_LIST_HEAD(&hw->list);
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list_add_tail(&hw->list, &lmh_dcvs_hw_list);
|
||||
mutex_unlock(&lmh_dcvs_list_access);
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static const struct of_device_id limits_dcvs_match[] = {
|
||||
{ .compatible = "qcom,msm-hw-limits", },
|
||||
{},
|
||||
};
|
||||
|
||||
static struct platform_driver limits_dcvs_driver = {
|
||||
.probe = limits_dcvs_probe,
|
||||
.driver = {
|
||||
.name = KBUILD_MODNAME,
|
||||
.of_match_table = limits_dcvs_match,
|
||||
},
|
||||
};
|
||||
builtin_platform_driver(limits_dcvs_driver);
|
||||
Loading…
Reference in New Issue
Block a user