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disp: msm: dsi: program DSI_PHY_CMN_CTRL_4 register

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For some phy ver 4 chipsets, DSI_PHY_CMN_CTRL_4 needs to be programmed
in normal power up sequence. This change adds support to program the
same based on minor phy version.

Change-Id: I68bed48ca671f540efafd13f8d56c7e90de8b25c
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
This commit is contained in:
Ritesh Kumar 2019-05-24 11:20:53 +05:30 committed by Gerrit - the friendly Code Review server
parent 06f8bcc142
commit d9448326ce
1 changed files with 7 additions and 0 deletions
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7
msm/dsi/dsi_phy_hw_v4_0.c
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@ -165,6 +165,7 @@ void dsi_phy_hw_v4_0_enable(struct dsi_phy_hw *phy,
u32 const timeout_us = 1000;
struct dsi_phy_per_lane_cfgs *timing = &cfg->timing;
u32 data;
u32 minor_ver = 0;
bool less_than_1500_mhz = false;
u32 vreg_ctrl_0 = 0;
u32 glbl_str_swi_cal_sel_ctrl = 0;
@ -204,6 +205,12 @@ void dsi_phy_hw_v4_0_enable(struct dsi_phy_hw *phy,
/* turn off resync FIFO */
DSI_W32(phy, DSIPHY_CMN_RBUF_CTRL, 0x00);
/* program CMN_CTRL_4 for minor_ver 2 chipsets*/
minor_ver = DSI_R32(phy, DSIPHY_CMN_REVISION_ID0);
minor_ver = minor_ver & (0xf0);
if (minor_ver == 0x20)
DSI_W32(phy, DSIPHY_CMN_CTRL_4, 0x04);
/* Configure PHY lane swap */
dsi_phy_hw_v4_0_lane_swap_config(phy, &cfg->lane_map);