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clk: meson: meson8b: Fix the vclk_div{1, 2, 4, 6, 12}_en gate bits

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[ Upstream commit 8bb629cfb28f4dad9d47f69249366e50ae5edc25 ]

The DIV{1,2,4,6,12}_EN bits are actually located in HHI_VID_CLK_CNTL
register:
- HHI_VID_CLK_CNTL[0] = DIV1_EN
- HHI_VID_CLK_CNTL[1] = DIV2_EN
- HHI_VID_CLK_CNTL[2] = DIV4_EN
- HHI_VID_CLK_CNTL[3] = DIV6_EN
- HHI_VID_CLK_CNTL[4] = DIV12_EN

Update the bits accordingly so we will enable the bits in the correct
register once we switch these clocks to be mutable.

Fixes: 6cb57c678b ("clk: meson: meson8b: add the read-only video clock trees")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
Link: https://lore.kernel.org/r/20200417184127.1319871-4-martin.blumenstingl@googlemail.com
Signed-off-by: Sasha Levin <sashal@kernel.org>
This commit is contained in:
Martin Blumenstingl 2020-04-17 20:41:26 +02:00 committed by Greg Kroah-Hartman
parent ecb9a8068b
commit dd47c98992
1 changed files with 5 additions and 5 deletions
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10
drivers/clk/meson/meson8b.c
View File

@ -1207,7 +1207,7 @@ static struct clk_regmap meson8b_vclk_in_en = {
static struct clk_regmap meson8b_vclk_div1_gate = { static struct clk_regmap meson8b_vclk_div1_gate = {
.data = &(struct clk_regmap_gate_data){ .data = &(struct clk_regmap_gate_data){
.offset = HHI_VID_CLK_DIV, .offset = HHI_VID_CLK_CNTL,
.bit_idx = 0, .bit_idx = 0,
}, },
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
@ -1237,7 +1237,7 @@ static struct clk_fixed_factor meson8b_vclk_div2_div = {
static struct clk_regmap meson8b_vclk_div2_div_gate = { static struct clk_regmap meson8b_vclk_div2_div_gate = {
.data = &(struct clk_regmap_gate_data){ .data = &(struct clk_regmap_gate_data){
.offset = HHI_VID_CLK_DIV, .offset = HHI_VID_CLK_CNTL,
.bit_idx = 1, .bit_idx = 1,
}, },
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
@ -1267,7 +1267,7 @@ static struct clk_fixed_factor meson8b_vclk_div4_div = {
static struct clk_regmap meson8b_vclk_div4_div_gate = { static struct clk_regmap meson8b_vclk_div4_div_gate = {
.data = &(struct clk_regmap_gate_data){ .data = &(struct clk_regmap_gate_data){
.offset = HHI_VID_CLK_DIV, .offset = HHI_VID_CLK_CNTL,
.bit_idx = 2, .bit_idx = 2,
}, },
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
@ -1297,7 +1297,7 @@ static struct clk_fixed_factor meson8b_vclk_div6_div = {
static struct clk_regmap meson8b_vclk_div6_div_gate = { static struct clk_regmap meson8b_vclk_div6_div_gate = {
.data = &(struct clk_regmap_gate_data){ .data = &(struct clk_regmap_gate_data){
.offset = HHI_VID_CLK_DIV, .offset = HHI_VID_CLK_CNTL,
.bit_idx = 3, .bit_idx = 3,
}, },
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){
@ -1327,7 +1327,7 @@ static struct clk_fixed_factor meson8b_vclk_div12_div = {
static struct clk_regmap meson8b_vclk_div12_div_gate = { static struct clk_regmap meson8b_vclk_div12_div_gate = {
.data = &(struct clk_regmap_gate_data){ .data = &(struct clk_regmap_gate_data){
.offset = HHI_VID_CLK_DIV, .offset = HHI_VID_CLK_CNTL,
.bit_idx = 4, .bit_idx = 4,
}, },
.hw.init = &(struct clk_init_data){ .hw.init = &(struct clk_init_data){