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clk: qcom: Add support for divider flags and table

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The clk-divider module in the clock framework provides support
for different kinds of dividers such as power-of-two and discrete
table based dividers. clk-regmap-divider module which adds regmap
support to the clk-divider doesn't handle the flags and table
parameters in the clk-divider that enables these divider types.
This change adds those two parameters to the clk-regmap-divider
struct and passes them to the clk-divider appropriately.

Change-Id: I0f9a923a62786b19264c45bbcf2400292ed7e61f
Signed-off-by: Rajkumar Subbiah <rsubbia@codeaurora.org>
This commit is contained in:
Rajkumar Subbiah 2017-07-14 16:53:28 -04:00 committed by David Collins
parent 50661feab0
commit e3688042c0
2 changed files with 18 additions and 12 deletions
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18
drivers/clk/qcom/clk-regmap-divider.c
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@ -1,6 +1,6 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2014, The Linux Foundation. All rights reserved.
* Copyright (c) 2014, 2016-2019, The Linux Foundation. All rights reserved.
*/
#include <linux/kernel.h>
@ -35,8 +35,10 @@ static long div_round_rate(struct clk_hw *hw, unsigned long rate,
{
struct clk_regmap_div *divider = to_clk_regmap_div(hw);
return divider_round_rate(hw, rate, prate, NULL, divider->width,
CLK_DIVIDER_ROUND_CLOSEST);
return divider_round_rate(hw, rate, prate, divider->table,
divider->width,
CLK_DIVIDER_ROUND_CLOSEST |
divider->flags);
}
static int div_set_rate(struct clk_hw *hw, unsigned long rate,
@ -46,8 +48,9 @@ static int div_set_rate(struct clk_hw *hw, unsigned long rate,
struct clk_regmap *clkr = &divider->clkr;
u32 div;
div = divider_get_val(rate, parent_rate, NULL, divider->width,
CLK_DIVIDER_ROUND_CLOSEST);
div = divider_get_val(rate, parent_rate, divider->table,
divider->width, CLK_DIVIDER_ROUND_CLOSEST |
divider->flags);
return regmap_update_bits(clkr->regmap, divider->reg,
(BIT(divider->width) - 1) << divider->shift,
@ -65,8 +68,9 @@ static unsigned long div_recalc_rate(struct clk_hw *hw,
div >>= divider->shift;
div &= BIT(divider->width) - 1;
return divider_recalc_rate(hw, parent_rate, div, NULL,
CLK_DIVIDER_ROUND_CLOSEST, divider->width);
return divider_recalc_rate(hw, parent_rate, div, divider->table,
CLK_DIVIDER_ROUND_CLOSEST | divider->flags,
divider->width);
}
const struct clk_ops clk_regmap_div_ops = {

4
drivers/clk/qcom/clk-regmap-divider.h
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@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2014, The Linux Foundation. All rights reserved.
* Copyright (c) 2014, 2016-2019, The Linux Foundation. All rights reserved.
*/
#ifndef __QCOM_CLK_REGMAP_DIVIDER_H__
@ -13,6 +13,8 @@ struct clk_regmap_div {
u32 reg;
u32 shift;
u32 width;
u32 flags;
const struct clk_div_table *table;
struct clk_regmap clkr;
};