mmc: sdhci_am654: Clear HISPD_ENA in some lower speed modes
According to the AM654x Data Manual[1], the setup timing in lower speed modes can only be met if the controller uses a falling edge data launch. To ensure this, the HIGH_SPEED_ENA (HOST_CONTROL[2]) bit should be cleared in default speed, SD high speed, MMC high speed, SDR12 and SDR25 speed modes. Use the sdhci writeb callback to implement this condition. [1] http://www.ti.com/lit/gpn/am6546 Section 5.10.5.16.1 Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Acked-by: Adrian Hunter <adrian.hunter@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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@ -994,6 +994,7 @@ config MMC_SDHCI_OMAP
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config MMC_SDHCI_AM654
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tristate "Support for the SDHCI Controller in TI's AM654 SOCs"
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depends on MMC_SDHCI_PLTFM && OF
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select MMC_SDHCI_IO_ACCESSORS
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help
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This selects the Secure Digital Host Controller Interface (SDHCI)
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support present in TI's AM654 SOCs. The controller supports
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@ -158,6 +158,27 @@ static void sdhci_am654_set_power(struct sdhci_host *host, unsigned char mode,
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sdhci_set_power_noreg(host, mode, vdd);
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}
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static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg)
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{
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unsigned char timing = host->mmc->ios.timing;
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if (reg == SDHCI_HOST_CONTROL) {
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switch (timing) {
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/*
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* According to the data manual, HISPD bit
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* should not be set in these speed modes.
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*/
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case MMC_TIMING_SD_HS:
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case MMC_TIMING_MMC_HS:
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case MMC_TIMING_UHS_SDR12:
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case MMC_TIMING_UHS_SDR25:
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val &= ~SDHCI_CTRL_HISPD;
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}
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}
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writeb(val, host->ioaddr + reg);
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}
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static struct sdhci_ops sdhci_am654_ops = {
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.get_max_clock = sdhci_pltfm_clk_get_max_clock,
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.get_timeout_clock = sdhci_pltfm_clk_get_max_clock,
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@ -165,6 +186,7 @@ static struct sdhci_ops sdhci_am654_ops = {
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.set_bus_width = sdhci_set_bus_width,
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.set_power = sdhci_am654_set_power,
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.set_clock = sdhci_am654_set_clock,
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.write_b = sdhci_am654_write_b,
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.reset = sdhci_reset,
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};
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