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soc: swr-mstr-ctrl: Move to CPU-1 FIFO for swr register read/write

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Both APSS and ADSP are accessing CPU-0 FIFO when CPS is enabled
during speaker playback. This causes underflow issue when accessing
wsa register from APSS. Move APSS to CPU-1 FIFO to resolve underflow
issue.

Change-Id: I5ed9143bc78757468fbe4bcc686196149ca521f2
Signed-off-by: Meng Wang <mengw@codeaurora.org>
This commit is contained in:
Meng Wang 2021-09-27 17:06:49 +08:00 committed by Gerrit - the friendly Code Review server
parent b0a827bef9
commit e92fbc265e
3 changed files with 33 additions and 16 deletions
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3
config/lahainaautoconf.h
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@ -1,5 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/* Copyright (c) 2020, The Linux Foundation. All rights reserved.
/* Copyright (c) 2020-2021, The Linux Foundation. All rights reserved.
*/
#define CONFIG_PINCTRL_LPI 1
@ -43,3 +43,4 @@
#define CONFIG_SND_SWR_HAPTICS 1
#define CONFIG_DIGITAL_CDC_RSC_MGR 1
#define CONFIG_AUXPCM_DISABLE 1
#define CONFIG_SWRM_VER_1P6 1

1
soc/swr-mstr-ctrl.c
View File

@ -54,7 +54,6 @@
#define ERR_AUTO_SUSPEND_TIMER_VAL 0x1
#define SWRM_INTERRUPT_STATUS_MASK 0x1FDFD
#define SWRM_LINK_STATUS_RETRY_CNT 100
#define SWRM_ROW_48 48

45
soc/swr-mstr-registers.h
View File

@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2015, 2018-2020 The Linux Foundation. All rights reserved.
* Copyright (c) 2015, 2018-2021 The Linux Foundation. All rights reserved.
*/
#ifndef _SWRM_REGISTERS_H
@ -18,24 +18,46 @@
#define MM_SYNC_CONFIG (SWRM_BASE+0x0108)
#define SWRM_COMP_NPL_PARAMS (SWRM_BASE+0x0120)
#define SWRM_INTERRUPT_STATUS (SWRM_BASE+0x0200)
#define SWRM_INTERRUPT_EN (SWRM_BASE+0x0204)
#define SWRM_INTERRUPT_CLEAR (SWRM_BASE+0x0208)
#define SWRM_INTERRUPT_STATUS_1 (SWRM_BASE+0x0220)
#define SWRM_INTERRUPT_EN_1 (SWRM_BASE+0x0224)
#define SWRM_INTERRUPT_CLEAR_1 (SWRM_BASE+0x0228)
#define SWRM_CPU1_INTERRUPT_EN (SWRM_BASE+0x0210)
#define SWRM_CPU1_INTERRUPT_EN_1 (SWRM_BASE+0x0230)
#define SWRM_CPU0_CMD_RESPONSE (SWRM_BASE+0x0250)
#define SWRM_CMD_FIFO_WR_CMD (SWRM_BASE+0x0300)
#define SWRM_CMD_FIFO_RD_CMD (SWRM_BASE+0x0304)
#define SWRM_CMD_FIFO_CMD (SWRM_BASE+0x0308)
#define SWRM_CMD_FIFO_STATUS (SWRM_BASE+0x030C)
#define SWRM_CMD_FIFO_CFG (SWRM_BASE+0x0314)
#define SWRM_CMD_FIFO_RD_FIFO (SWRM_BASE+0x0318)
#define SWRM_CPU1_CMD_FIFO_WR_CMD (SWRM_BASE+0x031C)
#define SWRM_CPU1_CMD_FIFO_RD_CMD (SWRM_BASE+0x0320)
#define SWRM_CPU1_CMD_FIFO_STATUS (SWRM_BASE+0x0328)
#define SWRM_CPU1_CMD_FIFO_RD_FIFO (SWRM_BASE+0x0334)
#ifdef CONFIG_SWRM_VER_1P6
#define SWRM_INTERRUPT_EN SWRM_CPU1_INTERRUPT_EN
#define SWRM_INTERRUPT_EN_1 SWRM_CPU1_INTERRUPT_EN_1
#define SWRM_CMD_FIFO_WR_CMD SWRM_CPU1_CMD_FIFO_WR_CMD
#define SWRM_CMD_FIFO_RD_CMD SWRM_CPU1_CMD_FIFO_RD_CMD
#define SWRM_CMD_FIFO_STATUS SWRM_CPU1_CMD_FIFO_STATUS
#define SWRM_CMD_FIFO_RD_FIFO SWRM_CPU1_CMD_FIFO_RD_FIFO
#define SWRM_INTERRUPT_STATUS_MASK 0x1FFDFD
#define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW 0x40000
#define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW 0x80000
#define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED 0x100000
#define SWRM_INTERRUPT_MAX 0x20
#else
#define SWRM_INTERRUPT_EN (SWRM_BASE+0x0204)
#define SWRM_INTERRUPT_EN_1 (SWRM_BASE+0x0224)
#define SWRM_CMD_FIFO_WR_CMD (SWRM_BASE+0x0300)
#define SWRM_CMD_FIFO_RD_CMD (SWRM_BASE+0x0304)
#define SWRM_CMD_FIFO_STATUS (SWRM_BASE+0x030C)
#define SWRM_CMD_FIFO_RD_FIFO (SWRM_BASE+0x0318)
#define SWRM_INTERRUPT_STATUS_MASK 0x1FDFD
#define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW 0x10
#define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW 0x20
#define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED 0x400
#define SWRM_INTERRUPT_MAX 0x11
#endif /* CONFIG_SWRM_VER_1P6 */
#define SWRM_CMD_FIFO_CMD (SWRM_BASE+0x0308)
#define SWRM_CMD_FIFO_CFG (SWRM_BASE+0x0314)
#define SWRM_CPU_NUM_ENTRIES_WR_CMD_FIFO (SWRM_BASE+0x0370)
#define SWRM_CPU0_SW_INTERRUPT_SET (SWRM_BASE+0x0374)
#define SWRM_CPU0_SW_MESSAGE0 (SWRM_BASE+0x0384)
@ -82,13 +104,10 @@
#define SWRM_INTERRUPT_STATUS_NEW_SLAVE_ATTACHED 0x2
#define SWRM_INTERRUPT_STATUS_CHANGE_ENUM_SLAVE_STATUS 0x4
#define SWRM_INTERRUPT_STATUS_MASTER_CLASH_DET 0x8
#define SWRM_INTERRUPT_STATUS_RD_FIFO_OVERFLOW 0x10
#define SWRM_INTERRUPT_STATUS_RD_FIFO_UNDERFLOW 0x20
#define SWRM_INTERRUPT_STATUS_WR_CMD_FIFO_OVERFLOW 0x40
#define SWRM_INTERRUPT_STATUS_CMD_ERROR 0x80
#define SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION 0x100
#define SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH 0x200
#define SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED 0x400
#ifdef CONFIG_SWRM_VER_1P1
#define SWRM_INTERRUPT_STATUS_NEW_SLAVE_AUTO_ENUM_FINISHED 0x800
@ -107,8 +126,6 @@
#define SWRM_INTERRUPT_STATUS_EXT_CLK_STOP_WAKEUP 0x10000
#define SWRM_INTERRUPT_MAX 0x11
#define SWRM_COMP_PARAMS_WR_FIFO_DEPTH 0x00007C00
#define SWRM_COMP_PARAMS_RD_FIFO_DEPTH 0x000F8000
#endif /* _SWRM_REGISTERS_H */