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Revert "disp: msm: dsi: Add DSI PLL support for 7nm_v4_1 arch"

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This reverts commit a965033fba.

Change-Id: Ifb3d9b1a10a28cd281459174a9291fea79ec781d
Signed-off-by: Naresh Kumar Lingagalla <quic_nlingaga@quicinc.com>
This commit is contained in:
Naresh Kumar Lingagalla 2022-07-07 10:11:26 +05:30
parent a965033fba
commit ed8c317940
4 changed files with 2 additions and 22 deletions
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1
config/konadisp.conf
View File

@ -11,4 +11,3 @@ export CONFIG_QCOM_MDSS_PLL=y
export CONFIG_MSM_SDE_ROTATOR=y
export CONFIG_MSM_SDE_ROTATOR_EVTLOG_DEBUG=y
export CONFIG_DRM_SDE_RSC=y
export CONFIG_DISPLAY_BUILD=y

5
msm/dsi/dsi_pll.c
View File

@ -1,7 +1,5 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
@ -23,7 +21,6 @@ static int dsi_pll_clock_register(struct platform_device *pdev,
switch (pll_res->pll_revision) {
case DSI_PLL_5NM:
case DSI_PLL_7NM_V4_1:
rc = dsi_pll_clock_register_5nm(pdev, pll_res);
break;
case DSI_PLL_10NM:
@ -153,8 +150,6 @@ int dsi_pll_init(struct platform_device *pdev, struct dsi_pll_resource **pll)
if (!strcmp(label, "dsi_pll_5nm"))
pll_res->pll_revision = DSI_PLL_5NM;
else if (!strcmp(label, "dsi_pll_7nm_v4_1"))
pll_res->pll_revision = DSI_PLL_7NM_V4_1;
else if (!strcmp(label, "dsi_pll_10nm"))
pll_res->pll_revision = DSI_PLL_10NM;
else

3
msm/dsi/dsi_pll.h
View File

@ -1,7 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */
/*
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Copyright (c) 2020, The Linux Foundation. All rights reserved.
*/
@ -56,7 +54,6 @@ struct lpfr_cfg {
enum {
DSI_PLL_5NM,
DSI_PLL_7NM_V4_1,
DSI_PLL_10NM,
DSI_UNKNOWN_PLL,
};

15
msm/dsi/dsi_pll_5nm.c
View File

@ -1,7 +1,5 @@
// SPDX-License-Identifier: GPL-2.0-only
/*
* Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
*
* Copyright (c) 2016-2021, The Linux Foundation. All rights reserved.
*/
@ -293,13 +291,6 @@ static inline bool dsi_pll_5nm_is_hw_revision(
true : false;
}
static inline bool dsi_pll_7nm_v4_1_is_hw_revision(
struct dsi_pll_resource *rsc)
{
return (rsc->pll_revision == DSI_PLL_7NM_V4_1) ?
true : false;
}
static inline int pll_reg_read(void *context, unsigned int reg,
unsigned int *val)
{
@ -2600,8 +2591,7 @@ int dsi_pll_clock_register_5nm(struct platform_device *pdev,
dsi0pll_vco_clk.priv = pll_res;
dsi0pll_shadow_vco_clk.priv = pll_res;
if (dsi_pll_5nm_is_hw_revision(pll_res) ||
dsi_pll_7nm_v4_1_is_hw_revision(pll_res)) {
if (dsi_pll_5nm_is_hw_revision(pll_res)) {
dsi0pll_vco_clk.min_rate = 600000000;
dsi0pll_vco_clk.max_rate = 5000000000;
dsi0pll_shadow_vco_clk.min_rate = 600000000;
@ -2670,8 +2660,7 @@ int dsi_pll_clock_register_5nm(struct platform_device *pdev,
dsi1pll_vco_clk.priv = pll_res;
dsi1pll_shadow_vco_clk.priv = pll_res;
if (dsi_pll_5nm_is_hw_revision(pll_res) ||
dsi_pll_7nm_v4_1_is_hw_revision(pll_res)) {
if (dsi_pll_5nm_is_hw_revision(pll_res)) {
dsi1pll_vco_clk.min_rate = 600000000;
dsi1pll_vco_clk.max_rate = 5000000000;
dsi1pll_shadow_vco_clk.min_rate = 600000000;