msm: cvp: Relocate CVP HW PC control
To avoid CVP SMMU fault during CVP warm/cold boot. Change-Id: I393d99c5b0227b7a695c4910f5186b2e5bd00209 Signed-off-by: George Shen <sqiao@codeaurora.org>
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@ -3987,15 +3987,6 @@ static int __iris_power_on(struct iris_hfi_device *device)
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device->intr_status = 0;
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enable_irq(device->cvp_hal_data->irq);
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/*
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* Hand off control of regulators to h/w _after_ enabling clocks.
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* Note that the GDSC will turn off when switching from normal
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* (s/w triggered) to fast (HW triggered) unless the h/w vote is
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* present. Since Iris isn't up yet, the GDSC will be off briefly.
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*/
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if (__enable_hw_power_collapse(device))
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dprintk(CVP_ERR, "Failed to enabled inter-frame PC\n");
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return rc;
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fail_enable_clks:
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@ -4166,7 +4157,7 @@ static void power_off_iris2(struct iris_hfi_device *device)
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static inline int __resume(struct iris_hfi_device *device)
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{
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int rc = 0;
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u32 flags = 0, reg_gdsc, reg_cbcr;
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u32 flags = 0, reg_gdsc, reg_cbcr, loop = 10;
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if (!device) {
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dprintk(CVP_ERR, "Invalid params: %pK\n", device);
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@ -4201,6 +4192,29 @@ static inline int __resume(struct iris_hfi_device *device)
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}
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__setup_ucregion_memory_map(device);
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/*
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* Hand off control of regulators to h/w _after_ enabling clocks.
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* Note that the GDSC will turn off when switching from normal
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* (s/w triggered) to fast (HW triggered) unless the h/w vote is
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* present. Since Iris isn't up yet, the GDSC will be off briefly.
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*/
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if (__enable_hw_power_collapse(device))
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dprintk(CVP_ERR, "Failed to enabled inter-frame PC\n");
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while (loop) {
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reg_gdsc = __read_register(device, CVP_CC_MVS1_GDSCR);
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if (reg_gdsc & 0x80000000) {
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usleep_range(100, 200);
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loop--;
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} else {
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break;
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}
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}
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if (!loop)
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dprintk(CVP_ERR, "fail to power off CORE during resume\n");
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/* Wait for boot completion */
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rc = __boot_firmware(device);
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if (rc) {
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@ -220,4 +220,5 @@
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#define CVP_CC_MVS0C_GDSCR (CVP_CC_BASE_OFFS + 0xBF8)
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#define CVP_CC_MVS1C_GDSCR (CVP_CC_BASE_OFFS + 0xC98)
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#define CVP_CC_MVS1C_CBCR (CVP_CC_BASE_OFFS + 0xCD4)
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#define CVP_CC_MVS1_GDSCR (CVP_CC_BASE_OFFS + 0xD98)
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#endif
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