Add debug registers to dump in the event of sync timeout for qsmmuv2.
Change-Id: I18cc3296e74ca0e2cb6f68f8aca67032d493410b
Signed-off-by: Prakash Gupta <guptap@codeaurora.org>
qsmmuv500_iova_to_phys checks for out of bound iova and skips ECATS
operations. While this is optimal, this also skips resuming stalled CB.
As part of S1 context fault handling iova_to_phys is followed by tlb
invalidation and sync. With context bank in stall state, the sync
operation will timeout.
Example:
arm-smmu: FAR = 0x000102325429beb4
arm-smmu: PAR = 0x0000000000000000
arm-smmu: FSR = 0x40000402 [TF R SS ]
arm-smmu: ECATS: address out of bounds: 0x000102325429beb4
arm-smmu: ECATS: address out of bounds: 0x000102325429beb4
arm-smmu: TLB sync timed out -- SMMU may be deadlocked
Call trace:
qsmmuv500_tlb_sync_timeout+0x360
__arm_smmu_tlb_sync+0x2b4
arm_smmu_tlb_sync_context+0x4c
arm_smmu_tlb_inv_context_s1+0x1ec
arm_smmu_context_fault+0xb84
irq_thread_fn+0x44
irq_thread+0x160
kthread+0x16c
ret_from_fork+0x10
Fix this by resuming the context bank before bailing out for out of bound
iova.
Change-Id: I754b38a3761869a5f0c00688211d26f1b0f47eec
Signed-off-by: Prakash Gupta <guptap@codeaurora.org>
The macros used for the page numbers do not accurately reflect the
offsets into the implementation defined register space, so update
them accordingly, and use page 7, or implementation defined page 5
for the ARM_SMMU_STATS_SYNC_INV_TBU_ACK register.
Change-Id: I14d2ce69d971f5ff93c2b2ca1f28ec5882169106
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
Print SSD info in the context fault handler. This is useful to
differentiate transaction generated within SMMU to those from actual
clients.
While we are at it, also move SID print before we start ATOS operations.
Sometime it's observed that if system triggers panic before fault handler
completes ATOS operations then the SID info is not printed. SID info has
been found to be must in order to identify the master. So print it before
we start ATOS operation.
Change-Id: I1391686510ef8d61bf11b83102c884b5fa433abd
Signed-off-by: Prakash Gupta <guptap@codeaurora.org>
add a debugfs interface under /sys/kernel/debug/iommu/capturebus
to support capture bus for smmuv500.
Change-Id: Ibf2a2daf87941387c1b3f990f05d86a1cd4dbfff
Signed-off-by: Vijayanand Jitta <vjitta@codeaurora.org>
[guptap@codeaurora.org: refactored implementation]
Signed-off-by: Prakash Gupta <guptap@codeaurora.org>
add a debugfs interface to support testbus also add an interface for
dumping testbus information, module parameters tcu_testbus_sel and
tbu_testbus_sel can be used for selecting different testbuses to dump
on tcu and tbu respectively.
Change-Id: I1bf420db053458b2ce1f43dc544c0776a3f4d176
Signed-off-by: Vijayanand Jitta <vjitta@codeaurora.org>
[isaacm@codeaurora.org: introduced CONFIG_ARM_SMMU_TESTBUS_DEBUGFS]
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
[guptap@codeaurora.org: resolved merge conflict]
Signed-off-by: Prakash Gupta <guptap@codeaurora.org>
There are IOMMU domains that require use of both the upper and
lower portions of the IOVA space. To fulfill this requirement,
add support to the ARM SMMU driver to correctly configure a few
registers when initializing a context bank, as well as use the
correct set of page tables when handling IOVAs.
Change-Id: I9845354845495601de83bf946c96c36f2346ceb7
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
qsmmuv500_tlb_sync_timeout() uses for_each_set_bit() to iterate
through the TBU IDs. However, for_each_set_bit() operates on
unsigned longs, while tbu_ids is a u32 variable. Change the type
of tbu_ids to unsigned long.
Change-Id: If59eedebb21d388f864a0e2579f8af6bb1fc0b75
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
Certain SMMU implementations depend on implementation specific
settings to ensure that translations for a group of SMMU masters
work properly, so add a function to determine if a master belongs
in a particular IOMMU group based on implementation defined
settings.
Also, wire up the QSMMUV500 implementation of this hook, leaving
the arm_smmu_arch_ops structure completely unused. Since it has
been superseded by the implementation framework, remove the
remaining support for it.
Change-Id: I53b1b014be187757c6e48e57f23cc9732103f890
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
Certain SMMU implementations may need to follow certain
procedures prior to having their devices removed, so
add support for implementation specific removals.
Also, migrate the QSMMUV500 device removal function to utilize
the newly added implementation specific removal hook. This makes
it so that there are no users of the device_remove() hook in the
arm_smmu_arch_ops structure, so remove it.
Change-Id: I6143fee5744ebec2090e74337f6fce99e23c5cf0
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
Certain SMMU implementation, such as the QSMMUV500 model, have
hardware that can be used to collect information that is useful
for debugging adversarial scenarios, such as TLB sync timeouts.
Add support for collecting information for debugging TLB sync
timeouts, as well as triggering the SMMU HW to perform a
translation for verification purpose, and wire up the QSMMUV500
implementations of these hooks. In doing so, there are no
users of the iova_to_phys_hard() and tlb_sync_timeout() hooks
in the arm_smmu_arch_ops structure, so remove these fields.
Change-Id: I61df57e82f3058a7e8a09f4df1fe147a71ae2fc3
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
Some SMMU implementations, such as the QSMMUV500 model, may
need to program a specific context bank, in addition to the
initial context bank programming. Thus, add support for
implementation specific context bank initialization, and
migrate the QSMMUV500 context bank initialization to use
the new hook.
Consequently, as there are no current users of the
arm_smmu_arch_init_context_bank() hook, remove it.
Change-Id: Ia89420cc8b669a142b37bf4250c09b6aa3646172
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
Rework the QSMMUV500 initialization sequence, such that the
QSMMUV500 implementation initialization uses the existing
SMMU implementation architecture.
This means ensuring that all of the implementation specific
data structures are allocated as part of the initialization,
as well as ensuring that all of the TBUs have probed. Also,
move the logic for hardware version detection to the QSMMUV500
configuration probe function.
Consequently, there are now no users of the arm_smmu_arch_init()
and arm_smmu_arch_device_reset() hooks, so remove them.
Change-Id: I8ca82ef8ea821b9e2171f7dca707f4da6ce2c0d7
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
All of the implementation details related to the QSMMUV500 model
of the SMMU-V2 architecture currently reside in arm-smmu.c.
This clashes with the current ARM SMMU SW architecture, as
arm-smmu.c is meant to house architecture specific details,
and arm-smmu-[$VENDOR].c is meant to house vendor specific
implementation details about those architectures.
To prepare to move to comply with this architecture, migrate
the QSMMUV500 related logic to arm-smmu-qcom.c, as well as
export any shared data structures. This patch should not
introduce any functional changes.
Change-Id: I711e41e38cd35b6727faf5a399eefcf5db453612
Signed-off-by: Isaac J. Manjarres <isaacm@codeaurora.org>
The Qualcomm bootloaders leaves the IOMMU with stream mapping for
the display hardware to be able to read the framebuffer memory in DDR,
to continuously display a boot splash or to implement EFI framebuffer.
This patch implements support for implementations to pin stream mappings
and adds the code to the Qualcomm implementation for reading out the
stream mapping from the bootloader, with the result of maintaining the
display hardware's access to DDR until the context bank is enabled.
Heavily based on downstream implementation by Patrick Daly
<pdaly@codeaurora.org>.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: John Stultz <john.stultz@linaro.org>
Bug: 146449535
Link: https://lore.kernel.org/linux-arm-msm/20191226221709.3844244-4-bjorn.andersson@linaro.org/
Change-Id: Ic87cfac8d9e85095d9f8000b37627bf24dd79626
Add reset hook for sdm845 based platforms to turn off
the wait-for-safe sequence.
Understanding how wait-for-safe logic affects USB and UFS performance
on MTP845 and DB845 boards:
Qcom's implementation of arm,mmu-500 adds a WAIT-FOR-SAFE logic
to address under-performance issues in real-time clients, such as
Display, and Camera.
On receiving an invalidation requests, the SMMU forwards SAFE request
to these clients and waits for SAFE ack signal from real-time clients.
The SAFE signal from such clients is used to qualify the start of
invalidation.
This logic is controlled by chicken bits, one for each - MDP (display),
IFE0, and IFE1 (camera), that can be accessed only from secure software
on sdm845.
This configuration, however, degrades the performance of non-real time
clients, such as USB, and UFS etc. This happens because, with wait-for-safe
logic enabled the hardware tries to throttle non-real time clients while
waiting for SAFE ack signals from real-time clients.
On mtp845 and db845 devices, with wait-for-safe logic enabled by the
bootloaders we see degraded performance of USB and UFS when kernel
enables the smmu stage-1 translations for these clients.
Turn off this wait-for-safe logic from the kernel gets us back the perf
of USB and UFS devices until we re-visit this when we start seeing perf
issues on display/camera on upstream supported SDM845 platforms.
The bootloaders on these boards implement secure monitor callbacks to
handle a specific command - QCOM_SCM_SVC_SMMU_PROGRAM with which the
logic can be toggled.
There are other boards such as cheza whose bootloaders don't enable this
logic. Such boards don't implement callbacks to handle the specific SCM
call so disabling this logic for such boards will be a no-op.
This change is inspired by the downstream change from Patrick Daly
to address performance issues with display and camera by handling
this wait-for-safe within separte io-pagetable ops to do TLB
maintenance. So a big thanks to him for the change and for all the
offline discussions.
Without this change the UFS reads are pretty slow:
$ time dd if=/dev/sda of=/dev/zero bs=1048576 count=10 conv=sync
10+0 records in
10+0 records out
10485760 bytes (10.0MB) copied, 22.394903 seconds, 457.2KB/s
real 0m 22.39s
user 0m 0.00s
sys 0m 0.01s
With this change they are back to rock!
$ time dd if=/dev/sda of=/dev/zero bs=1048576 count=300 conv=sync
300+0 records in
300+0 records out
314572800 bytes (300.0MB) copied, 1.030541 seconds, 291.1MB/s
real 0m 1.03s
user 0m 0.00s
sys 0m 0.54s
Signed-off-by: Vivek Gautam <vivek.gautam@codeaurora.org>
Reviewed-by: Robin Murphy <robin.murphy@arm.com>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: Will Deacon <will@kernel.org>
(cherry picked from commit 759aaa10c76cbaaefc0670410fb2d54cf4ec10cc)
Signed-off-by: John Stultz <john.stultz@linaro.org>
Bug: 146449535
Change-Id: I19992dad55516fa0444c79d7f50363ef57633c97
