Fix of performance and stability issues on Intel NOR chips. It fixes:
1. Very low write performance on Sibley (perf tests demonstrated write
performance less than 100Kb/sec when it should be over 400Kb/sec).
2. Low erase performance. (perf tests on Sibleuy demonstrated erase
performance 246Kb/sec when it should be over 300Kb/sec).
3. Error on JFFS2 tests with CPU loading application when MTD returns
"block erase error: (status timeout)" To fix the issue it does the
following:
1. Removes the timeout tuning from inval_cache_and_wait_for_operation.
2. Waiting conditions in inval_cache_and_wait_for_operation now is
based on timer resolution
If timeout is lower than timer resolution then we do in cycle
"Checking the status"
udelay(1);
cond_resched();
If timeout is greater than timer resolution (probably erase
operation) We do the following
sleep for half of operation timeout and do in cycle the following
"Checking the status"
sleep for timer resolution
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Alexey Korolev <akorolev@infradead.org>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
o Add a flag MTD_BIT_WRITEABLE for devices that allow single bits to be
cleared.
o Replace MTD_PROGRAM_REGIONS with a cleared MTD_BIT_WRITEABLE flag for
STMicro and Intel Sibley flashes with internal ECC. Those flashes
disallow clearing of single bits, unlike regular NOR flashes, so the
new flag models their behaviour better.
o Remove MTD_ECC. After the STMicro/Sibley merge, this flag is only set
and never checked.
Signed-off-by: Joern Engel <joern@wh.fh-wedel.de>
At least two flashes exists that have the concept of a minimum write unit,
similar to NAND pages, but no other NAND characteristics. Therefore, rename
the minimum write unit to "writesize" for all flashes, including NAND.
Signed-off-by: Joern Engel <joern@wh.fh-wedel.de>
This allows for much better abstraction and separation of the XIP and
non-XIP cases with their own specific implementations. This fixes the
case where a timeout was tripped on in the XIP case by the code that
was meant for the non-XIP case only.
This also makes for a nice code reduction.
Signed-off-by: Nicolas Pitre <nico@cam.org>
CC: "Alexey, Korolev" <alexey.korolev@intel.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
The patch below fixes a potential starvation issue that can arise when
there is contention on a chip during a period when a process is
currently writing to it. The starvation is avoided by conditionally
rescheduling when the chip is left in a state usable by other processes.
Signed-off-by: Josh Boyer <jdub@us.ibm.com>
Signed-off-by: Tom Gall <tom_gall@vnet.ibm.com>
Signed-off-by: David Woodhouse <dwmw2@infradead.org>
Fix a kernel oops for Intel P30 flashes, where the wait queue head was not
initialized for the flchip struct, which in turn caused a crash at the
first read operation.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: <stable@kernel.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
I found an issue in cfi_cmdset0001.c. It is related to cache region
invalidation in the buffered write procedure.
The code performs cache invalidation from "cmd_addr" to "cmd_adr + len" in
do_write_buffer() while we modify region from "adr" to "adr+len".
This issue affects writes + reads of data by small chunks.
Signed-off-by: Nicolas Pitre <nico@cam.org>
Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
This is the drivers/mtd part of the big kfree cleanup patch.
Remove pointless checks for NULL prior to calling kfree() in drivers/mtd/.
Signed-off-by: Jesper Juhl <jesper.juhl@gmail.com>
Cc: David Woodhouse <dwmw2@infradead.org>
Acked-by: Joern Engel <joern@wohnheim.fh-wedel.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Change to the extended cfi table parsing for Intel NOR flash that uses
the info in the extended table to 'walk' the table rather than using
hard coding for various primary extended query table version numbers.
From: Jared Hulbert <jaredeh@gmail.com>
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
While this might be useful for all supported flash types, it is mandatory
for proper JFFS2 support with Sibley flash.
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This updates the Primary Vendor-Specific Extended Query parsing to
version 1.4 in order to get the information about the Configurable
Programming Mode regions implemented in the Sibley flash, as well as
selecting the appropriate write command code.
This flash does not behave like traditional NOR flash when writing data.
While mtdblock should just work, further changes are needed for JFFS2 use.
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This includes improved error handling/reporting plus some other
message cleanups.
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Modify Amd/Fujitsu CFI NOR flash primary vendor extension table revision
check to recognize version 1.4. Verified the existing driver can
handle version 1.4 chips without additional info from 1.4 extended table.
Move the primary vendor extension table revision check from common file
to the 3 CFI chip driver files, since the data structures and revisions
handled by those data structures are specific to the chip driver.
Modify the error message printed when the revision is unknown to be a
KERN_ERR instead of WARNING since this will cause mtd to ignore the chip.
Signed-off-by: Todd Poynor <tpoynor@mvista.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This reworks the XIP locking to make sure no lock primitive is ever
called from XIP disabled paths even if in theory they should not
cause any reschedule. Relying on the current spinlock implementation
is rather fragile and not especially clean from an abstraction pov.
The recent RT work makes it even more obvious.
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
to make sure the flash is in array mode whenever we're about to
reboot. This is especially useful to allow "soft" reboot to work
which consists of branching back into the bootloader.
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Skip jiffy delay after each block lock/unlock for Intel CFI flash
with the "Instant Individual Block Locking" feature bit set.
Signed-off-by: Todd Poynor <tpoynor@mvista.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
oldstate has to be reset to FL_READY after sync completion.
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
The change makes the code endianess aware and replaces the bogus
nested loop to or the status flags together.
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
This enables support for reading, writing and locking so called
"Protection Registers" present on some flash chips.
A subset of them are pre-programmed at the factory with a
unique set of values. The rest is user-programmable.
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Initial git repository build. I'm not bothering with the full history,
even though we have it. We can create a separate "historical" git
archive of that later if we want to, and in the meantime it's about
3.2GB when imported into git - space that would just make the early
git days unnecessarily complicated, when we don't have a lot of good
infrastructure for it.
Let it rip!
