While I was going through the crypto users recently, I noticed this
bogus kmap in sunrpc. It's totally unnecessary since the crypto
layer will do its own kmap before touching the data. Besides, the
kmap is throwing the return value away.
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: David S. Miller <davem@davemloft.net>
If the tail SKB fits into the window, it is still
benefitical to defer until the goal percentage of
the window is available. This give the application
time to feed more data into the send queue and thus
results in larger TSO frames going out.
Patch from Dmitry Yusupov <dima@neterion.com>.
Signed-off-by: David S. Miller <davem@davemloft.net>
Thanks to Stephane, we've now worked out the real cause of the
`Linux will not boot on simulator' problem. Turns out it's a stack
overflow because the stack pointer wasn't being initialised properly
in boot_head.S (it was being initialised to the lowest instead of the
highest address of the stack, so the first push started to overwrite
data in the BSS).
Signed-off-by: Peter Chubb <peterc@gelato.unsw.edu.au>
Signed-off-by: Tony Luck <tony.luck@intel.com>
Re-order release_region calls in i810_probe to properly unwind preceding
allocations.
Signed-off-by: John W. Linville <linville@tuxdriver.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
The purpose of this patch:
- Adopt the DMA API (jazzsonic, macsonic & core driver).
- Adopt the driver model (macsonic).
This part was cribbed from jazzsonic. As a consequence, macsonic once
again works as a module. Driver model is also used by the DMA calls.
- Support 16 bit cards (macsonic & core driver, also affects jazzsonic)
This code was adapted from the mac68k linux 2.2 kernel, where it has
languished for a long time.
- Support more 32-bit mac cards (macsonic)
Also from mac68k repo.
- Zero-copy buffer handling (core driver)
Provides a nice performance improvement. The new algorithm incidentally
helped to replace the old Jazz DMA code.
The patch was tested on a variety of macs (several 32-bit quadra built-in
NICs, a 16-bit LC PDS NIC and a 16-bit comm-slot NIC), and also on MIPS
Jazz.
Signed-off-by: Finn Thain <fthain@telegraphics.com.au>
Acked-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
As SII reports that only original 3112's are affected by M15W quirk,
This patch adds SIL_FLAG_MOD15WRITE to selectively apply M15W quirk
depending on chipsets. As of yet, we don't know exactly which PCI IDs
are for original 3112, so M15W quirk is applied to all except for 3512
and 3124. Once more info is avaliable, we can change some of these
sil_3112_m15w's to sil_3112.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
[PATCH libata-dev-2.6:upstream] implement ata_poll_qc_complete and use it in polling functions
Previously, libata polling functions turned irq back on and completed
qc commands without holding host lock. This creates a race condition
between the polling task and interrupts from other ports on the same
host set or spurious interrupt from itself.
This patch implements ata_poll_qc_complete which enables irq and
completes qc atomically and convert all polling functions.
Note: atapi_packet_task() didn't use to turn irq back on or clear
ATA_FLAG_NOINTR on error exits. This patch makes it use
ata_poll_qc_complete which does both.
Note: With this change, ALL invocations of ata_qc_complete() are now
done under host_set lock.
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Interrupts from devices sharing the same IRQ could cause
ata_host_intr to finish commands being processed by atapi_packet_task
if the commands are using ATA_PROT_ATAPI_NODATA or ATA_PROT_ATAPI_DMA
protocol. This is because libata interrupt handler is unaware that
interrupts are not expected during that period. This patch adds
ATA_FLAG_NOINTR flag to tell the interrupt handler that we're not
expecting interrupts.
Note that once proper HSM is implemented for interrupt-driven PIO,
this should be merged into it and this flag will be removed.
ahci.c is a different kind of beast, so it's left alone.
* The following drivers use ata_qc_issue_prot and ata_interrupt, so
changes in libata core will do.
ata_piix sata_sil sata_svw sata_via sata_sis sata_uli
* The following drivers use ata_qc_issue_prot and custom intr handler.
They need this change to work correctly.
sata_nv sata_vsc
* The following drivers use custom issue function and intr handler.
Currently all custom issue functions don't support ATAPI, so this
change is irrelevant, updated for consistency and to avoid later
mistakes.
sata_promise sata_qstor sata_sx4
Signed-off-by: Tejun Heo <htejun@gmail.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Patch: fix wrong HD activity control by ahci driver
The ahci driver 1.0 sets the SActive bit on every transaction,
causing the LED to light up. The SActive bit is used only for
native command queuing (NCQ) which the current driver version
doesn't implement. Resetting the SActive bit is the device's
responsibility (by sending a "Set Device Bits FIS" to the
host adapter) but this is not required in response to
non-NCQ commands, and (most) devices don't. Thus the LED
stays always on. This patch fixes the LED behavior.
Spec references:
http://www.intel.com/technology/serialata/pdf/rev1_1.pdf, sec. 3.3.13, 5.5.1
http://www.serialata.org/docs/serialata10a.pdfhttp://www.intel.com/design/storage/papers/25266401.pdf
Signed-off-by: Martin.Wilck@fujitsu-siemens.com
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
The Promise TX4200 is a 4-port SATA controller based on the PDC40519 chip. It
meets the description of the 20319, so just a simple ID needs to be added to
support this hardware. Thanks to Martin Povolný for testing.
Signed-off-by: Daniel Drake <dsd@gentoo.org>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Otto Meier recently submitted a patch to support the PDC40718 chip (marketed
as SATA300 TX4, a 4-port SATA controller).
Signed-off-by: Otto Meier <gf435@gmx.net>
Signed-off-by: Daniel Drake <dsd@gentoo.org>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Description:
After calling the completion callback, the libata error handler might be
running and getting atapi sense data. Clearing the ATA_QCFLAG_ACTIVE flag
at this point might interfere with the libata error handler.
Changes:
- Clear the ATA_QCFLAG_ACTIVE flag before calling the completion callback
(and also before the error handler)
- Add some comment
Signed-off-by: Albert Lee <albertcc@tw.ibm.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
[PATCH] [NET] mv643xx: add workaround for HW checksum generation bug
The hardware checksum generator on the mv64xxx occasionally generates
an incorrect checksum. This patch works around the issue and enables
hardware checksum generation.
Signed-off-by: Dale Farnsworth <dale@farnsworth.org>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Most importantly, remove bogus BUG() in receive path.
Signed-off-by: Patrick McHardy <kaber@trash.net>
Signed-off-by: David S. Miller <davem@davemloft.net>
An incorrect check made it bail out before doing anything.
Signed-off-by: Patrick McHardy <kaber@trash.net>
Signed-off-by: David S. Miller <davem@davemloft.net>
Plug a race in TSC synchronization
We need to do tsc_sync_wait() before the CPU is set online to prevent
multiple CPUs from doing it in parallel - which won't work because TSC
sync has global unprotected state.
Signed-off-by: Andi Kleen <ak@suse.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
I'm trying to get the nmi working with my laptop (IBM ThinkPad G41) and after
debugging it a while, I found that the nmi code doesn't want to set it up for
this particular CPU.
Here I have:
$ cat /proc/cpuinfo
processor : 0
vendor_id : GenuineIntel
cpu family : 15
model : 4
model name : Mobile Intel(R) Pentium(R) 4 CPU 3.33GHz
stepping : 1
cpu MHz : 3320.084
cache size : 1024 KB
physical id : 0
siblings : 2
core id : 0
cpu cores : 1
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 3
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni
monitor ds_cpl est tm2 cid xtpr
bogomips : 6642.39
processor : 1
vendor_id : GenuineIntel
cpu family : 15
model : 4
model name : Mobile Intel(R) Pentium(R) 4 CPU 3.33GHz
stepping : 1
cpu MHz : 3320.084
cache size : 1024 KB
physical id : 0
siblings : 2
core id : 0
cpu cores : 1
fdiv_bug : no
hlt_bug : no
f00f_bug : no
coma_bug : no
fpu : yes
fpu_exception : yes
cpuid level : 3
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge
mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe pni
monitor ds_cpl est tm2 cid xtpr
bogomips : 6637.46
And the following code shows:
$ cat linux-2.6.13-rc6/arch/i386/kernel/nmi.c
[...]
void setup_apic_nmi_watchdog (void)
{
switch (boot_cpu_data.x86_vendor) {
case X86_VENDOR_AMD:
if (boot_cpu_data.x86 != 6 && boot_cpu_data.x86 != 15)
return;
setup_k7_watchdog();
break;
case X86_VENDOR_INTEL:
switch (boot_cpu_data.x86) {
case 6:
if (boot_cpu_data.x86_model > 0xd)
return;
setup_p6_watchdog();
break;
case 15:
if (boot_cpu_data.x86_model > 0x3)
return;
Here I get boot_cpu_data.x86_model == 0x4. So I decided to change it and
reboot. I now seem to have a working NMI. So, unless there's something know
to be bad about this processor and the NMI. I'm submitting the following
patch.
Signed-off-by: Steven Rostedt <rostedt@goodmis.org>
Acked-by: Zwane Mwaikambo <zwane@arm.linux.org.uk>
Acked-by: Mikael Pettersson <mikpe@csd.uu.se>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
Hi,
Patch Description:
This patch incorporates the following hardware fixes required
for Xframe II adapter.
1. New values to program the dtx_control register.
2. Disable memory controller interrupts(MC_INTR) since these
are now monitored thru' a poll routine.
3. Don't reset an XframeII card on an ECC double-bit error(It
can recover).
4. Save/restore PCI config space before/after a reset irrespective
of Xframe I or II card.
5. Bumped up the driver version no. to 2.0.3.1
Please review the patch and apply the same if it looks ok.
Signed-off-by: Ravinandan Arakali <ravinandan.arakali@neterion.com>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
Now that all tms380 devices have a valid
struct device with dma_mask, remove dmalimit from tmsdev_init().
Kconfig: depend tms380tr and madgemc on MCA.
abyss.c, proteon.c, skisa.c, tmspci.c, tms380tr.h:
remove dmalimit parameter from tmsdev_init().
tms380tr.c: use device->dma_mask instead of dmalimit.
madgemc.c: move to new MCA API using struct device.
Signed-off-by: Jochen Friedrich <jochen@scram.de>
Signed-off-by: Jeff Garzik <jgarzik@pobox.com>
This bug could cause oopses and page state corruption, because ncpfs
used the generic page-cache symlink handlign functions. But those
functions only work if the page cache is guaranteed to be "stable", ie a
page that was installed when the symlink walk was started has to still
be installed in the page cache at the end of the walk.
We could have fixed ncpfs to not use the generic helper routines, but it
is in many ways much cleaner to instead improve on the symlink walking
helper routines so that they don't require that absolute stability.
We do this by allowing "follow_link()" to return a error-pointer as a
cookie, which is fed back to the cleanup "put_link()" routine. This
also simplifies NFS symlink handling.
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
The current calling conventions for ->follow_link() are already fairly
complex.
What we have is
1) you can return -error; then you must release nameidata yourself
and ->put_link() will _not_ be called.
2) you can do nd_set_link(nd, ERR_PTR(-error)) and return 0
3) you can do nd_set_link(nd, path) and return 0
4) you can return 0 (after having moved nameidata yourself)
jffs2 follow_link() is broken - it has an exit where it returns
-EIO and leaks nameidata.
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
sparc_ksyms.c used to declare weak alias to several gcc intrinsics. It
doesn't work with gcc4 anymore - it wants a declaration for the thing
we are aliasing to and that's not going to happen for something like
.mul, etc. Replaced with direct injection of weak alias on the assembler
level - .weak <alias> followed by <alias> = <aliased>; that works on all
gcc versions.
Signed-off-by: Al Viro <viro@parcelfarce.linux.theplanet.co.uk>
Signed-off-by: David S. Miller <davem@davemloft.net>
GCC 4.x really dislikes the games we are playing in
unaligned.c, and the cleanest way to fix this is to
move things into assembler.
Noted by Al Viro.
Signed-off-by: David S. Miller <davem@davemloft.net>
GLIBC 2.3.4 and later changed the STT_REGISTER macro to
STT_SPARC_REGISTER, so we need to cope with that somehow.
Original patch from fabbione, reposted by Ben Collins.
Signed-off-by: David S. Miller <davem@davemloft.net>
A problem was reported by Grant Grundler on an HP rx8620 using IOX
Core LAN partno(A7109-6) 5701 copper NIC. The tg3 driver mistakenly
detects this NIC as having a SerDes PHY and link does not come up as a
result.
The problem was caused by an incorrectly programmed eeprom that set the
NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER bit in the NIC_SRAM_DATA_CFG location.
This patch will override the NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER bit if a
valid PHY ID is read from the MII registers on older 570x chips where
the MII interface is not used on SerDes chips. On newer chips such as
the 5780 that use MII for both copper and SerDes, SerDes detection must
rely on the eeprom.
This patch will make the SerDes detection identical to versions 3.25 and
older.
Signed-off-by: Michael Chan <mchan@broadcom.com>
Acked-by: Grant Grundler <iod00d@hp.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
There's no point in having the host name duplicated between
the mmc_host structure and the encapsulated class device
structure.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Create a mmc_host class to allow enumeration of MMC host controllers
even though they have no card(s) inserted.
Patch based on work by Pierre Ossman.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
