Add null check for plane state pointer before
dereferencing it.
Change-Id: Ic66efd11a70162ffe65c2137a5f19688314c45a5
Signed-off-by: Prashant Singh <prasin@codeaurora.org>
Write to hardware registers should be exposed for only debug
purpose. Hence use CONFIG_DYNAMIC_DEBUG to restrict register
writes only for debug defconfig.
Change-Id: I0b67b46a69920f6620570ace9d4faf732076126d
Signed-off-by: Lakshmi Narayana Kalavala <lkalaval@codeaurora.org>
The change adds a check to make sure the length of bytes being
copied don't exceed the size of the destination buffer
causing an overflow.
Change-Id: Ib3ca3705e4179ccda1af11279e96e167baee6a3b
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Add configuration data to handle 10bpp 3:1
compression ratio based on hardware recommended
settings.
CRs-Fixed: 2325207
Change-Id: I7086dc235e0063a79c661fa8cee77d4e47e9c826
Signed-off-by: Fuad Hossain <fhossain@codeaurora.org>
Ensure that the dp dsc peak pxl rate does not
exceed the maximum supported by the sink device.
If the mode's peak pxl rate per slice exceeds the
max, mark the mode as invalid.
CRs-Fixed: 2325207
Change-Id: Ic8904c759b8621c3aff258206599e1994f70e26e
Signed-off-by: Fuad Hossain <fhossain@codeaurora.org>
The line buffer bit depth is used as part of dp
dsc calculations. Read the max supported line buf
bit depth supported by sink, and use that
restriction as part of the dsc calculations.
CRs-Fixed: 2325207
Change-Id: I4c995acad5f484edd1b438bdbf6c145b2d35ee41
Signed-off-by: Fuad Hossain <fhossain@codeaurora.org>
As per hardware recommendation, DMA pipe
width is reduced to 2880, while vig
pipewidth is 4096.
Change-Id: I70dbd44b4883f49879686003ba1fe9694434daab
Signed-off-by: Jayaprakash <jmadiset@codeaurora.org>
Disable double buffer vsync configuration while
enabling clk and cmd state switch sequence. Leaving
this configuration in enable state may cause different
issues for different state switch. Clock state switch
may see a vsync delay for solver disable. Command
state switch may not update the vsync source.
Change-Id: I910fc7e33a20a04b602435020173d85a4ee926d1
Signed-off-by: Dhaval Patel <pdhaval@codeaurora.org>
For DSI PHY timing of version 4, adds the missing configuation
of phy_clk_params and updates some extra clock parameters.
The less precision during calculation is fixed, which is caused by
not exactly following PHY timing document.
Change-Id: Ibb75d4d3e5b4a5979ff4a85dba1accf3677a6584
Signed-off-by: Yujun Zhang <yujunzhang@codeaurora.org>
Remove dividers that are not recommended for DSI DPHY mode
when setting up the clock tree for the DSI pixel clock.
Change-Id: I2563a35ece541c1f5b46c72af7bd2cc79e72a90e
Signed-off-by: Aravind Venkateswaran <aravindh@codeaurora.org>
This change updates the DSI PHY sequence for Kona target as
per latest HW team recommendation.
Change-Id: I110cc5044d2676ade58f947b3efca53d1d72753c
Signed-off-by: Satya Rama Aditya Pinapala <psraditya30@codeaurora.org>
Force a disconnect if the simulation client disables simulation
before disconnecting from the simulated sink. This ensures that
the driver will not erroneously attempt AUX transactions in
subsequent interactions after simulation is disabled.
Change-Id: Ibc581deafe46753c514bccc70ba5c953c8d49bd8
Signed-off-by: Tatenda Chipeperekwa <tatendac@codeaurora.org>
Report the HDR10+ sink capability and payload data when user-space
reads the "hdr" debugfs node. Also add support for reporting HDR
properties for MST sessions via the new "hdr_mst" debugfs node.
Write support for this node was removed since it updated the
connector state in an inconsistent way, therefore HDR updates must
come from the atomic commit.
Change-Id: I58af4042c1b3198eb78fe413728104071cf50caf
Signed-off-by: Steve Cohen <cohens@codeaurora.org>
Branch address offset for TCS sleep/wake has
changed for lito, add changes to support it.
Change-Id: Id938c4c85df17f6709b9533ff737cf5a0186bc09
Signed-off-by: Animesh Kishore <animeshk@codeaurora.org>
Improve dp mst simulator mode by adding support
for up to 8 connectors, the ability to add and
remove ports dynamically, and allowing for
different EDIDs for each connector.
CRs-Fixed: 2459530
Change-Id: I945e3292a7e5150ab7a6bbe0addc4f4f46d58e82
Signed-off-by: Fuad Hossain <fhossain@codeaurora.org>
New version of the gamut block has been introduced with changes to
the scale/offset programming. Change updates the minor version for
the feature.
Change-Id: I62597a9d229e13e10e0ac0f1183b2db2b0b2a575
Continuous splash enabled displays are identified by reading
the MDP ctl registers. DSI cont-splash init settings are
called based on this. Additionally, DSI reads the DSI-CTL
scratch register set by bootloader to detect cont-splash.
This change removes the redundant mechanism in DSI to
detect cont-splash.
Change-Id: Ic58be1e62eda239fcea5e82d9d356905dc552a73
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
This change adds proper null checks after using
kcalloc and returns early to avoid accessing null ptr.
Change-Id: I948ad37eb120e00c5f6e3ae2e3b967819cbd233b
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
This change takes a snapshot from 4.14 to 4.19 as of
commit 47d149c31967 ("drm/msm/sde: Add null pointer
sanity checks").
Change-Id: Ib40428c562c3561c8a20d9849f16d13151496005
Signed-off-by: Samantha Tran <samtran@codeaurora.org>
This change adds support for dynamic switching of dsi clocks
to avoid RF interference issues. DSI PHY V4 support is added.
Change-Id: I5bdbd6d2916692087c0192d23c8e7598238f161f
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
Signed-off-by: Yujun Zhang <yujunzhang@codeaurora.org>
Fixes suspend-resume not working after switching dsi clk for
video mode. While switching the dsi clk, FLAG_SEAMLESS_DYN_CLK
is set leading to enable dsi clks which causes extra refcount.
Add check for command mode.
Change-Id: I814eb9c87daf387b5d57c5a3dddf7ae1e60fe784
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
Currently the dynamic bit clock switch trigger for command mode
is supported via sysfs node. This might lead to unnecessary
race conditions, when dsi driver is enabling the dsi bit clock
as part of commit and at the same time if bit rate change via
sysfs happens. So make the trigger happens via kernel mode set
call as done for video mode.
Change-Id: I17acb408d2b6dbd6fa41994e56262e31e43d088b
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
Signed-off-by: Yujun Zhang <yujunzhang@codeaurora.org>
This change adds support for dynamic switching of dsi clocks
to avoid RF interference issues. Also with dynamic dsi clock
switch feature coming into picture, now populate the supported
refresh rate as list instead of providing a range. Modify the
logic to enumerate all the modes in dsi driver, taking dynamic
bit clocks, resolutions and refresh rates into account.
Change-Id: I5b6e62bc935cf2234bdd96fcb3c7537b4e735fff
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
Signed-off-by: Yujun Zhang <yujunzhang@codeaurora.org>
Add support for 7nm DSI PLL shadow clocks, which will be
used during dynamic dsi clock switch and dfps feature.
Change-Id: I870f961c7af4d404e61b45a4ad860ffb0e71ae7c
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
Signed-off-by: Yujun Zhang <yujunzhang@codeaurora.org>
Signed-off-by: Ray Zhang <rayz@codeaurora.org>
Add support for 10nm DSI PLL shadow clocks, which will be
used during dynamic dsi clock switch and dfps feature.
Change-Id: Ib61bc5dcb5304bc1e3c7568c1419737580da3c88
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
Signed-off-by: Yujun Zhang <yujunzhang@codeaurora.org>
Signed-off-by: Ray Zhang <rayz@codeaurora.org>
During atomic_check phase the encoder_mask is taken
from old crtc->state leading to wrong validation.
Fix it by taking the encoder_mask from new crtc state.
Change-Id: Ifcfc4bee887168d8208ffdafb1cf5ea4c4473796
Signed-off-by: Veera Sundaram Sankaran <veeras@codeaurora.org>
Existing cwb implementation waits for WB done interrupt in
wait_for_commit_done API call. This serializes the cwb commit
and causes frame trigger delay on primary display. MDSS hw allows
to trigger the cwb frame when previous frame is in-progress. This
change updates driver to allow parallel frame trigger for cwb
enabled display. It releases frame N cwb output buffer in frame
N+1 wait_for_commit done call.
Change-Id: Id4f2a0cc78a3f24a1b5ce96dc907780246768dbf
Signed-off-by: Raviteja Tamatam <travitej@codeaurora.org>
