lisa/android_kernel_xiaomi_sm8350
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4 Commits

Author SHA1 Message Date
Ralf Baechle
47740eb887 MIPS: Enable CLO / CLZ instructions via separate CPU property 
This is useful for IDT RC32332, RC32334 and NEC VR5500 processors which do
not implement the full MIPS32 / MIPS64 architecture.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2009-05-14 13:50:26 +01:00
David Daney
47d979eca3 MIPS: Hook Cavium OCTEON cache init into cache.c 
Follow precedent of other boards, and hook-up the CPU specific cache
init.

Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com>
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2009-01-11 09:57:22 +00:00
Ralf Baechle
c46b302b94 MIPS: New feature test macro cpu_has_mips_r 
cpu_has_mips_r is true if a processor is MIPS32 or MIPS64, any architecture
revision.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2008-10-30 14:44:33 +00:00
Ralf Baechle
384740dc49 MIPS: Move headfiles to new location below arch/mips/include 
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
 2008-10-11 16:18:52 +01:00