Commit Graph

283 Commits

Author SHA1 Message Date
Michael S. Tsirkin
5f6164f309 [PATCH] add asm-generic/mman.h
Make new MADV_REMOVE, MADV_DONTFORK, MADV_DOFORK consistent across all
arches.  The idea is to make it possible to use them portably even before
distros include them in libc headers.

Move common flags to asm-generic/mman.h

Signed-off-by: Michael S. Tsirkin <mst@mellanox.co.il>
Cc: Roland Dreier <rolandd@cisco.com>
Cc: Badari Pulavarty <pbadari@us.ibm.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-02-15 15:32:22 -08:00
Michael S. Tsirkin
f822566165 [PATCH] madvise MADV_DONTFORK/MADV_DOFORK
Currently, copy-on-write may change the physical address of a page even if the
user requested that the page is pinned in memory (either by mlock or by
get_user_pages).  This happens if the process forks meanwhile, and the parent
writes to that page.  As a result, the page is orphaned: in case of
get_user_pages, the application will never see any data hardware DMA's into
this page after the COW.  In case of mlock'd memory, the parent is not getting
the realtime/security benefits of mlock.

In particular, this affects the Infiniband modules which do DMA from and into
user pages all the time.

This patch adds madvise options to control whether memory range is inherited
across fork.  Useful e.g.  for when hardware is doing DMA from/into these
pages.  Could also be useful to an application wanting to speed up its forks
by cutting large areas out of consideration.

Signed-off-by: Michael S. Tsirkin <mst@mellanox.co.il>
Acked-by: Hugh Dickins <hugh@veritas.com>
Cc: Michael Kerrisk <mtk-manpages@gmx.net>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-02-14 16:09:34 -08:00
Maciej W. Rozycki
9cf8ff9644 [MIPS] Fix CPU type bitmasks for MIPS III, IV and V.
Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-14 19:13:25 +00:00
Ralf Baechle
fbb6b3a4ac [MIPS] Get rid of kludgery needed to keep stdargs of old compilers working.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-14 19:13:25 +00:00
Ralf Baechle
3218357c94 [MIPS] More uaccess.h fixes with gcc >= 4.0.1.
From Richard Sandiford <richard@codesourcery.com>:
    
This patch caused a miscompilation of the restore_gp_regs() block
in restore_sigcontext().  This was in a 32-bit kernel compiled with
GCC CVS head.
    
restore_gp_regs() copies 64-bit user fields into 32-bit variables,
and in this combination, the new __get_user_asm_ll32() clobbers too
many registers.  It says:
    
/*
 * Get a long long 64 using 32 bit registers.
 */
{									\
	__asm__ __volatile__(						\
	"1:	lw	%1, (%3)				\n"	\
	"2:	lw	%D1, 4(%3)				\n"	\
	"	move	%0, $0					\n"	\
	"3:	.section	.fixup,\"ax\"			\n"	\
	"4:	li	%0, %4					\n"	\
	"	move	%1, $0					\n"	\
	"	move	%D1, $0					\n"	\
	"	j	3b					\n"	\
	"	.previous					\n"	\
	"	.section	__ex_table,\"a\"		\n"	\
	"	" __UA_ADDR "	1b, 4b				\n"	\
	"	" __UA_ADDR "	2b, 4b				\n"	\
	"	.previous					\n"	\
	: "=r" (__gu_err), "=&r" (val)					\
	: "0" (0), "r" (addr), "i" (-EFAULT));				\
}

and this requires val (%1) to be a 64-bit value.  In the case I saw,
gcc was using $3 for the 32-bit val, and wasn't expecting $4 to be
clobbered.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-14 19:13:24 +00:00
Atsushi Nemoto
41700e7399 [MIPS] Add protected_blast_icache_range, blast_icache_range, etc.
Add blast_xxx_range(), protected_blast_xxx_range() etc. for common
use.  They are built by __BUILD_BLAST_CACHE_RANGE().
Use protected_cache_op() macro for various protected_ routines.
Output code should be logically same.
    
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-14 19:13:24 +00:00
Ralf Baechle
359bbd42a5 [MIPS] Fold non-__mips64 case into CONFIG_32BIT case.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-14 19:13:23 +00:00
Ralf Baechle
f32ec77b42 [MIPS] RM200: Give RM200 it's own timex.h.
So we can get rid of config.h and the #ifdef crapola in the generic
timex.h.
    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-14 19:13:23 +00:00
Linus Torvalds
f564c5fe29 Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus 2006-02-08 09:58:27 -08:00
Atsushi Nemoto
b887d3f2c6 [MIPS] Add 'const' to readb and friends
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

---
2006-02-08 17:52:27 +00:00
Ralf Baechle
72bf891421 [MIPS] Wire up new syscalls.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

---
2006-02-08 17:52:25 +00:00
Ralf Baechle
40ac5d479b [MIPS] Make do_signal return void.
It's return value is ignored everywhere.
    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

---
2006-02-08 17:52:25 +00:00
Ralf Baechle
7b3e2fc847 [MIPS] Add support for TIF_RESTORE_SIGMASK.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

---
2006-02-08 17:52:24 +00:00
Al Viro
290f10ae42 [PATCH] mips: namespace pollution - mem_... -> __mem_... in io.h
A pile of internal functions use only inside mips io.h has names starting
with mem_... and clashing with names in drivers; renamed to __mem_....

Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2006-02-08 01:03:06 -05:00
Al Viro
1b8623545b [PATCH] remove bogus asm/bug.h includes.
A bunch of asm/bug.h includes are both not needed (since it will get
pulled anyway) and bogus (since they are done too early).  Removed.

Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
2006-02-07 20:56:35 -05:00
Sergei Shtylylov
f09678af51 [MIPS] TX49x7: Fix reporting of the CPU name and PCI clock
I've noticed that PCI clock was incorrectly reported as 66 MHz while being
mere 33 MHz on RBTX4937 board -- this was due to the different encoding of
the PCI divisor field in CCFG register between TX4927 and TX4937 chips...
    
Also, RBTX49x7 was printed out as a CPU name (e.g., "CPU is RBTX4937");
and some debug printk() were duplicating each other...
    
Signed-off-by: Konstantin Baydarov <kbaidarov@ru.mvista.com>
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-07 13:30:26 +00:00
Atsushi Nemoto
c226f2601f [MIPS] TX49 MFC0 bug workaround
If mfc0 $12 follows store and the mfc0 is last instruction of a
page and fetching the next instruction causes TLB miss, the result
of the mfc0 might wrongly contain EXL bit.
    
ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008
    
Workaround: mask EXL bit of the result or place a nop before mfc0.  It
doesn't harm to always clear those bits, so we change the code to do so.
    
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-07 13:30:26 +00:00
Ralf Baechle
1e32ceeca2 [MIPS] MIPS R2 optimized endianess swapping.
From Franck Bui-Huu <vagabon.xyz@gmail.com> with modifications by me.
    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-07 13:30:25 +00:00
Ralf Baechle
7e5b24ac75 [MIPS] Remove buggy inline version of memscan.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-07 13:30:25 +00:00
Atsushi Nemoto
d4264f1839 [MIPS] Remove wrong __user tags.
This fixes sparse warnings 'dereference of noderef expression'.
    
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-07 13:30:25 +00:00
Ralf Baechle
2caf190002 [MIPS] Cleanup fls implementation.
fls was the only called of flz, so fold flz into fls, same for the
__ilog2 call.  Delete the now unused flz function.
    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-07 13:30:24 +00:00
Ralf Baechle
2e66fe24d6 [MIPS] local_irq_restore wasn't safe to be used in other macros mode.
It always left the assembler in reorder mode possibly causing disaster.
    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-07 13:30:24 +00:00
Atsushi Nemoto
76f072a46f [MIPS] Build blast_cache routines from template
Build blast_xxx, blast_xxx_page, blast_xxx_page_indexed from template.
Easier to maintaina and saves 300 lines.  Generated code should be
unchanged.
    
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-07 13:30:24 +00:00
Sergei Shtylylov
492fd5f2fd [MIPS] Au1200: Make KGDB compile
AMD Au1200 SOC just doesn't have UART3, so KGDB won't even compile for it
as is, here's the fix to make KGDB use UART1.
    
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-07 13:30:23 +00:00
Sergei Shtylylov
6fe2a5681f [MIPS] TX49x7: Fix timer register #define's
Fix the #define's for TX4927/37 timer reg's to match the datasheets (those
    
Signed-off-by: Konstantin Baydarov <kbaidarov@mvista.com>
Signed-off-by: Sergei Shtylyov <sshtylyov@mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-07 13:30:23 +00:00
Ralf Baechle
4feb8f8f45 [MIPS] Bullet proof uaccess.h against 4.0.1 miss-compilation.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-07 13:30:23 +00:00
Ralf Baechle
dd2f18fe5a [MIPS] Nevada support for SGI O2.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-07 13:30:22 +00:00
Ralf Baechle
c011db451b [MIPS] CPU definitions for Cobalt.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-07 13:30:22 +00:00
Ralf Baechle
11ed6d5bb0 [MIPS] Rename include/asm-mips/cobalt to include/asm-mips/mach-cobalt.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-07 13:30:22 +00:00
Ralf Baechle
fcdb27ad1d [MIPS] Rename _machine_power_off to pm_power_off so the kernel builds again.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-07 13:30:22 +00:00
Ralf Baechle
05faa7b758 [MIPS] Fix C version of ssnop to use the right opcode.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-07 13:30:21 +00:00
Al Viro
f5a61d0c13 [PATCH] death of get_thread_info/put_thread_info
{get,put}_thread_info() were introduced in 2.5.4 and never
had been called by anything in the tree.

Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-01-12 09:08:59 -08:00
Al Viro
75bb07e788 [PATCH] mips: task_stack_page()
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-01-12 09:08:59 -08:00
Al Viro
40bc9c671a [PATCH] mips: task_pt_regs()
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-01-12 09:08:58 -08:00
akpm@osdl.org
198e2f1811 [PATCH] scheduler cache-hot-autodetect
)

From: Ingo Molnar <mingo@elte.hu>

This is the latest version of the scheduler cache-hot-auto-tune patch.

The first problem was that detection time scaled with O(N^2), which is
unacceptable on larger SMP and NUMA systems. To solve this:

- I've added a 'domain distance' function, which is used to cache
  measurement results. Each distance is only measured once. This means
  that e.g. on NUMA distances of 0, 1 and 2 might be measured, on HT
  distances 0 and 1, and on SMP distance 0 is measured. The code walks
  the domain tree to determine the distance, so it automatically follows
  whatever hierarchy an architecture sets up. This cuts down on the boot
  time significantly and removes the O(N^2) limit. The only assumption
  is that migration costs can be expressed as a function of domain
  distance - this covers the overwhelming majority of existing systems,
  and is a good guess even for more assymetric systems.

  [ People hacking systems that have assymetries that break this
    assumption (e.g. different CPU speeds) should experiment a bit with
    the cpu_distance() function. Adding a ->migration_distance factor to
    the domain structure would be one possible solution - but lets first
    see the problem systems, if they exist at all. Lets not overdesign. ]

Another problem was that only a single cache-size was used for measuring
the cost of migration, and most architectures didnt set that variable
up. Furthermore, a single cache-size does not fit NUMA hierarchies with
L3 caches and does not fit HT setups, where different CPUs will often
have different 'effective cache sizes'. To solve this problem:

- Instead of relying on a single cache-size provided by the platform and
  sticking to it, the code now auto-detects the 'effective migration
  cost' between two measured CPUs, via iterating through a wide range of
  cachesizes. The code searches for the maximum migration cost, which
  occurs when the working set of the test-workload falls just below the
  'effective cache size'. I.e. real-life optimized search is done for
  the maximum migration cost, between two real CPUs.

  This, amongst other things, has the positive effect hat if e.g. two
  CPUs share a L2/L3 cache, a different (and accurate) migration cost
  will be found than between two CPUs on the same system that dont share
  any caches.

(The reliable measurement of migration costs is tricky - see the source
for details.)

Furthermore i've added various boot-time options to override/tune
migration behavior.

Firstly, there's a blanket override for autodetection:

	migration_cost=1000,2000,3000

will override the depth 0/1/2 values with 1msec/2msec/3msec values.

Secondly, there's a global factor that can be used to increase (or
decrease) the autodetected values:

	migration_factor=120

will increase the autodetected values by 20%. This option is useful to
tune things in a workload-dependent way - e.g. if a workload is
cache-insensitive then CPU utilization can be maximized by specifying
migration_factor=0.

I've tested the autodetection code quite extensively on x86, on 3
P3/Xeon/2MB, and the autodetected values look pretty good:

Dual Celeron (128K L2 cache):

 ---------------------
 migration cost matrix (max_cache_size: 131072, cpu: 467 MHz):
 ---------------------
           [00]    [01]
 [00]:     -     1.7(1)
 [01]:   1.7(1)    -
 ---------------------
 cacheflush times [2]: 0.0 (0) 1.7 (1784008)
 ---------------------

Here the slow memory subsystem dominates system performance, and even
though caches are small, the migration cost is 1.7 msecs.

Dual HT P4 (512K L2 cache):

 ---------------------
 migration cost matrix (max_cache_size: 524288, cpu: 2379 MHz):
 ---------------------
           [00]    [01]    [02]    [03]
 [00]:     -     0.4(1)  0.0(0)  0.4(1)
 [01]:   0.4(1)    -     0.4(1)  0.0(0)
 [02]:   0.0(0)  0.4(1)    -     0.4(1)
 [03]:   0.4(1)  0.0(0)  0.4(1)    -
 ---------------------
 cacheflush times [2]: 0.0 (33900) 0.4 (448514)
 ---------------------

Here it can be seen that there is no migration cost between two HT
siblings (CPU#0/2 and CPU#1/3 are separate physical CPUs). A fast memory
system makes inter-physical-CPU migration pretty cheap: 0.4 msecs.

8-way P3/Xeon [2MB L2 cache]:

 ---------------------
 migration cost matrix (max_cache_size: 2097152, cpu: 700 MHz):
 ---------------------
           [00]    [01]    [02]    [03]    [04]    [05]    [06]    [07]
 [00]:     -    19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1)
 [01]:  19.2(1)    -    19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1)
 [02]:  19.2(1) 19.2(1)    -    19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1)
 [03]:  19.2(1) 19.2(1) 19.2(1)    -    19.2(1) 19.2(1) 19.2(1) 19.2(1)
 [04]:  19.2(1) 19.2(1) 19.2(1) 19.2(1)    -    19.2(1) 19.2(1) 19.2(1)
 [05]:  19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1)    -    19.2(1) 19.2(1)
 [06]:  19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1)    -    19.2(1)
 [07]:  19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1) 19.2(1)    -
 ---------------------
 cacheflush times [2]: 0.0 (0) 19.2 (19281756)
 ---------------------

This one has huge caches and a relatively slow memory subsystem - so the
migration cost is 19 msecs.

Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Ashok Raj <ashok.raj@intel.com>
Signed-off-by: Ken Chen <kenneth.w.chen@intel.com>
Cc: <wilder@us.ibm.com>
Signed-off-by: John Hawkes <hawkes@sgi.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-01-12 09:08:50 -08:00
Ingo Molnar
4dc7a0bbeb [PATCH] sched: add cacheflush() asm
Add per-arch sched_cacheflush() which is a write-back cacheflush used by
the migration-cost calibration code at bootup time.

Signed-off-by: Ingo Molnar <mingo@elte.hu>
Cc: Nick Piggin <nickpiggin@yahoo.com.au>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-01-12 09:08:49 -08:00
Ralf Baechle
7043ad4f4c MIPS: R2: Try to bulletproof instruction_hazard against miss-compilation.
Gcc has a tradition of misscompiling the previous construct using the
address of a label as argument to inline assembler.  Gas otoh has the
annoying difference between la and dla which are only usable for 32-bit
rsp. 64-bit code, so can't be used without conditional compilation.
The alterantive is switching the assembler to 64-bit code which happens
to work right even for 32-bit code ...
    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-01-10 13:39:08 +00:00
Maxime Bizon
15265251c5 MIPS: R2: Fix local_irq_save()
local_irq_restore uses di which saves the whole status content, not
just the IE bit resulting in  local_irq_restore() to fail.  This only
happens if both CONFIG_CPU_MIPSR2 and CONFIG_IRQ_CPU are enabled.
    
Signed-off-by: Maxime Bizon <mbizon@freebox.fr>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-01-10 13:39:08 +00:00
Al Viro
d56efda451 MIPS: Namespace pollution: dump_regs() -> elf_dump_regs()
dump_regs() is used by a bunch of drivers for their internal stuff;
renamed mips instance (one that is seen in system-wide headers)
to elf_dump_regs()
    
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-01-10 13:39:08 +00:00
Sergei Shtylyov
c5c64e2283 MIPS: Au1550: Fix OHCI memory map size
USB OpenHCI host controller on Au1550 only decodes memory addresses from
0x14020000 to 0x1407FFFF according to the databook, which gives 0x60000
(on the prior Au1x00 chips the map size was 1MB).
    
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Acked-by: Jordan Crouse <jordan.crouse@amd.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-01-10 13:39:07 +00:00
Ralf Baechle
29ce2c765c Update Yoichi Yuasa's email address.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-01-10 13:39:07 +00:00
Ralf Baechle
0401572a9b MIPS: Reorganize ISA constants strictly as bitmasks.
Signed-off-by: Ralf Baechle <ralf@ongar.mips.com>
2006-01-10 13:39:07 +00:00
Ralf Baechle
b4672d3729 MIPS: Introduce machinery for testing for MIPSxxR1/2.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-01-10 13:39:06 +00:00
Ralf Baechle
e7958bb90d MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-01-10 13:39:06 +00:00
Ralf Baechle
b2d28b7ea5 MIPS: Get rid of atomic_lock.
It was resulting in build errors for some configurations.
    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-01-10 13:39:06 +00:00
Ralf Baechle
264879576c MIPS: DSP: Put mask field into the right place.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-01-10 13:39:05 +00:00
Ralf Baechle
07a801def4 MIPS: DSP: Set all register masks to 0x3ff.
0x2ff was a typo and the value 0x1f of DSP_MASK was refering to an old
version of the documentation.
    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-01-10 13:39:04 +00:00
Atsushi Nemoto
f12555d24c MIPS: Fix mdelay(1) for 64bit kernel with HZ == 1000
mdelay(1) (i.e. udelay(1000)) does not work correctly due to overflow.
    
1000 * 0x004189374BC6A7f0 = 0x10000000000000180 (>= 2**64)
    
0x004189374BC6A7ef (0x004189374BC6A7f0 - 1) is OK and it is exactly
same as catchall case (0x8000000000000000UL / (500000 / HZ)).
    
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-01-10 13:39:04 +00:00
Ralf Baechle
6c35585273 MIPS: DSP: eleminate used_dsp.
used_dsp was meant to be used like used_math - but since the FPU context
is small and lazy context switching is a stupid idea on multiprocessors
this idea only got halfway implemented and those bits are were now
breaking ptrace.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-01-10 13:39:04 +00:00
Ralf Baechle
da2c9ed55b MIPS: DSP: Context switch the DSPcontrol register also.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-01-10 13:39:04 +00:00