Support dynamically config blur resolution to firmware.
Remove unused code for encoder aspect_ratio extradata.
Change-Id: Id2896ab943de4b676338b42bd4993d4057e960ac
Signed-off-by: Qiwei Liu <qiweil@codeaurora.org>
Entry field from clock data structure gets initialized with
codec data during state transition from MSM_VIDC_CORE_INIT_DONE
to MSM_VIDC_OPEN. When flush is called before this transaction,
it calls msm_clock_data_reset where mentioned field is getting
accessed, which results in uninitialized data access. Add state
check to ensure the command is handled in right sequence.
Change-Id: Ic98221cbfe465415d89a0e2891f8af65f584f1dc
Signed-off-by: Aniket Masule <amasule@codeaurora.org>
By calculating bitrate at each frame, we get a better estimate
of the BW requirements of the decode session. Thus improving
performance and power usage.
CRs-Fixed: 2451137
Change-Id: I22f0029bbb7d501340469a317e89de7eb34717c4
Signed-off-by: Chinmay Sawarkar <chinmays@codeaurora.org>
Use S32_MAX instead of U32_MAX for maximum ctrl val for
blur resolution, as ctrl val is s32.
Change-Id: Ie92f6ba831ffead2d56c9eee24917b8a42cdd564
Signed-off-by: Qiwei Liu <qiweil@codeaurora.org>
Move cbr plus variable to legacy cbr variable as
it is interfering with CVP usage.
Change-Id: If31f49858486e4295e7dfd9f47175e23c4078200
Signed-off-by: Darshana Patil <darshana@codeaurora.org>
Signed-off-by: Maheshwar Ajja <majja@codeaurora.org>
Regulator handoff causes the GDSC to turn off momentarily and resets
internal registers. As a result, TZ is unable to program secure
registers during Secure PIL load fails. Moving the handoff after
PIL load allows proper secure register programming and enables
secure sessions.
CRs-Fixed: 2450296
Change-Id: I32c7bf8726b51fdfa73b40819e8fdccdbbc0abe3
Signed-off-by: Chinmay Sawarkar <chinmays@codeaurora.org>
The structure vidc_hal_session_init_done is not being used,
so remove it.
Change-Id: Id4a577db117f98b18439245907765be5c9badc83
Signed-off-by: Maheshwar Ajja <majja@codeaurora.org>
Default UBWC configuration for LPDDR5 is corrected.
Highest Bank Bit is set to 16.
Change-Id: I0fb18279ae32d34a7f3bada6d05a72c5935430dd
Signed-off-by: Akshata Sahukar <asahukar@codeaurora.org>
video driver does not support TME format, so remove it.
Change-Id: Ica7656fc1758a007f0d20d0351a4cedb82b9a0ee
Signed-off-by: Maheshwar Ajja <majja@codeaurora.org>
Kona target supports two LTR frames encoding.
Fixing this capability in kona driver.
Handle resolution check correctly while setting
slice mode.
Change-Id: Iea6a041ecafb24da014832ecf2146088d4569a6f
CRs-Fixed: 2444064
Signed-off-by: Darshana Patil <darshana@codeaurora.org>
Video kernel snapshot before disabling msm/vidc compilation
from base kernel.
Change-Id: Id1178c3aca00706ad4822537f7f9a28141478771
Signed-off-by: Shivendra Kakrania <shiven@codeaurora.org>
This change brings msm vidc driver from base 4.19 kernel project.
It is the first source code snapshot from base kernel project.
Change-Id: I1d600c4e9459b9013f4b607890c52644f6d94f0c
Signed-off-by: Shivendra Kakrania <shiven@codeaurora.org>
