Commit Graph

171 Commits

Author SHA1 Message Date
Ralf Baechle
432bef2a31 [MIPS] Replace BARRIER with more appropriate hazard barrier.
This is the unchanged part 2 of Chris' hazard cleanup.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-09-27 13:37:54 +01:00
Ralf Baechle
a00f631018 [MIPS] c-r4k: Convert init functions from inline to __init.
With more recent compilers inline doesn't necessarily means a function
will always be inlined.  So leave that decission to the compiler and
make the function as __init.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-09-27 13:37:44 +01:00
Ralf Baechle
00932ba305 [MIPS] Make PROT_WRITE imply PROT_READ. 2006-09-27 13:37:42 +01:00
Atsushi Nemoto
f6502791d7 [MIPS] Do not use drop_mmu_context to flusing other task's VIPT I-cache.
c-r4k.c and c-sb1.c use drop_mmu_context() to flush virtually tagged
I-caches, but this does not work for flushing other task's icache.  This
is for example triggered by copy_to_user_page() called from ptrace(2).
Use indexed flush for such cases.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-09-27 13:37:37 +01:00
Ralf Baechle
585fa72493 [MIPS] Retire flush_icache_page from mm use.
On the 34K the redundant cache operations were causing excessive stalls
resulting in realtime code running on the second VPE missing its deadline.
For all other platforms this patch is just a significant performance
improvment as illustrated by below benchmark numbers.

Processor, Processes - times in microseconds - smaller is better
------------------------------------------------------------------------------
Host                 OS  Mhz null null      open slct sig  sig  fork exec sh
                             call  I/O stat clos TCP  inst hndl proc proc proc
--------- ------------- ---- ---- ---- ---- ---- ---- ---- ---- ---- ---- ----
25Kf      2.6.18-rc4     533 0.49 1.16 7.57 33.4 30.5 1.34 12.4 5497 17.K 54.K
25Kf      2.6.18-rc4-p   533 0.49 1.16 6.68 23.0 30.7 1.36 8.55 5030 16.K 48.K
4Kc       2.6.18-rc4      80 4.21 15.0 131. 289. 261. 16.5 258. 18.K 70.K 227K
4Kc       2.6.18-rc4-p    80 4.34 13.1 128. 285. 262. 18.2 258. 12.K 52.K 176K
34Kc      2.6.18-rc4      40 5.01 14.0 61.6 90.0 477. 17.9 94.7 29.K 108K 342K
34Kc      2.6.18-rc4-p    40 4.98 13.9 61.2 89.7 475. 17.6 93.7 8758 44.K 158K
BCM1480   2.6.18-rc4     700 0.28 0.60 3.68 5.92 16.0 0.78 5.08 931. 3163 15.K
BCM1480   2.6.18-rc4-p   700 0.28 0.61 3.65 5.85 16.0 0.79 5.20 395. 1464 8385
TX49-16K  2.6.18-rc3     197 0.73 2.41 19.0 37.8 82.9 2.94 17.5 4438 14.K 56.K
TX49-16K  2.6.18-rc3-p   197 0.73 2.40 19.9 36.3 82.9 2.94 23.4 2577 9103 38.K
TX49-32K  2.6.18-rc3     396 0.36 1.19 6.80 11.8 41.0 1.46 8.17 2738 8465 32.K
TX49-32K  2.6.18-rc3-p   396 0.36 1.19 6.82 10.2 41.0 1.46 8.18 1330 4638 18.K
    
Original patch by me with enhancements by Atsushi Nemoto.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
2006-09-27 13:37:34 +01:00
Ralf Baechle
df586d59a4 [MIPS] c-r4k: Typo fix.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-09-27 13:37:23 +01:00
Christoph Lameter
f06a96844a [PATCH] reduce MAX_NR_ZONES: fix MAX_NR_ZONES array initializations
Fix array initialization in lots of arches

The number of zones may now be reduced from 4 to 2 for many arches.  Fix the
array initialization for the zones array for all architectures so that it is
not initializing a fixed number of elements.

Signed-off-by: Christoph Lameter <clameter@sgi.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-09-26 08:48:46 -07:00
Atsushi Nemoto
f4dee85e2c [MIPS] sparsemem: fix crash in show_mem
With sparsemem, pfn should be checked by pfn_valid() before pfn_to_page().

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-13 21:26:22 +01:00
Thiemo Seufer
115f2a44e0 [MIPS] Print out TLB handler assembly for debugging.
Small update, using pr_debug and pr_info.

Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-13 21:26:16 +01:00
Yoichi Yuasa
2874fe5533 [MIPS] vr41xx: Replace magic number for P4K bit with symbol.
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-13 21:26:11 +01:00
Yoichi Yuasa
1058ecda9b [MIPS] vr41xx: Changed workaround to recommended method
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-13 21:26:11 +01:00
Atsushi Nemoto
565200a146 [MIPS] Do not count pages in holes with sparsemem
With some memory model other than FLATMEM, the single node can
contains some holes so there might be many invalid pages.  For
example, with two 256M memory and one 256M hole, some variables
(num_physpage, totalpages, nr_kernel_pages, nr_all_pages, etc.) will
indicate that there are 768MB on this system.  This is not desired
because, for example, alloc_large_system_hash() allocates too many
entries.
    
Use free_area_init_node() with counted zholes_size[] instead of
free_area_init().

For num_physpages, use number of ram pages instead of max_low_pfn.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-13 21:26:08 +01:00
Yoichi Yuasa
4e8ab36182 [MIPS] VR41xx: Set VR41_CONF_BP only for PrId 0x0c80.
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-13 21:26:06 +01:00
Ralf Baechle
fc5d2d279f [MIPS] Use the proper technical term for naming some of the cache macros.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-07-13 21:26:04 +01:00
Jörn Engel
6ab3d5624e Remove obsolete #include <linux/config.h>
Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de>
Signed-off-by: Adrian Bunk <bunk@stusta.de>
2006-06-30 19:25:36 +02:00
Ralf Baechle
2e78ae3f48 [MIPS] 74K: Assume it will also have an AR bit in config7
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-29 21:10:54 +01:00
Ralf Baechle
beab375a48 [MIPS] Treat CPUs with AR bit as physically indexed.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-29 21:10:54 +01:00
Atsushi Nemoto
a2c2bc4b26 [MIPS] MIPS32/MIPS64 S-cache fix and cleanup
Use blast_scache_range, blast_inv_scache_range for mips32/mips64 scache
routine.  Also initialize waybit for MIPS32/MIPS64 S-cache.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-29 21:10:54 +01:00
Chris Dearman
73f403527b [MIPS] Fix handling of 0 length I & D caches.
Don't ask.

Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-29 21:10:53 +01:00
Chris Dearman
9318c51acd [MIPS] MIPS32/MIPS64 secondary cache management
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-29 21:10:52 +01:00
Ralf Baechle
5deee2dbf4 [MIPS] Remove prototype for non-existing function.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-19 17:39:18 +01:00
Chad Reese
b1c231f5a5 [MIPS] Fix sparsemem support.
Move memory_present() in arch/mips/kernel/setup.c. When using sparsemem
extreme, this function does an allocate for bootmem. This would always
fail since init_bootmem hasn't been called yet.
    
Move memory_present after free_bootmem. This only marks actual memory
ranges as present instead of the entire address space.
    
Signed-off-by: Chad Reese  <creese@caviumnetworks.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-06 00:15:20 +01:00
Sergei Shtylyov
9370b35175 [MIPS] Save write-only Config.OD from being clobbered
Save the Config.OD bit from being clobbered by coherency_setup(). This
bit, when set, fixes various errata in the early steppings of Au1x00
SOCs.  Unfortunately, the bit was write-only on the most early of them.
In addition, also restore the bit after a wakeup from sleep.
    
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-06 00:15:13 +01:00
Kumba
44d921b246 [MIPS] Treat R14000 like R10000.
Signed-off-by: Joshua Kinard <kumba@gentoo.org>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-01 00:28:35 +01:00
Ralf Baechle
7f3f1d01a9 [MIPS] Fix deadlock on MP with cache aliases.
A proper fix would involve introducing the notion of shared caches but
at this stage of 2.6.17 that's going to be too intrusive and not needed
for current hardware; aside I think some discussion will be needed.

So for now on the affected SMP configurations which happen to suffer from
cache aliases we make use of the fact that a single cache will be shared
by all processors.  This solves the deadlock issue and will improve
performance by getting rid of the smp_call_function overhead.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-01 00:28:33 +01:00
Chris Dearman
c620953c32 [MIPS] Fix detection and handling of the 74K processor.
Nothing exciting; Linux just didn't know it yet so this is most adding
a value to a case statement.
    
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-01 00:28:30 +01:00
Nigel Stephens
98a41de99a [MIPS] Add missing 34K processor IDs
The 34K is very much like a 24K on steroids.
    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-06-01 00:28:30 +01:00
Atsushi Nemoto
3c68da798a [MIPS] Use __ffs() instead of ffs() for waybit calculation.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-19 04:14:30 +02:00
Ralf Baechle
7e3bfc7cfc [MIPS] Handle IDE PIO cache aliases on SMP.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-19 04:14:29 +02:00
Ralf Baechle
41c594ab65 [MIPS] MT: Improved multithreading support.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-19 04:14:28 +02:00
Atsushi Nemoto
67a3f6de93 [MIPS] Fix tx49_blast_icache32_page_indexed.
Fix the cache index value in tx49_blast_icache32_page_indexed().
This is a damage by de62893bc0 commit.

Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-19 04:14:21 +02:00
Ralf Baechle
f13b68e817 [MIPS] Fix CONFIG_LIMITED_DMA build.
This fix a build error for the Momentum Jaguar ATX eval board.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-19 04:14:19 +02:00
Ralf Baechle
91b05e6776 [MIPS] Fix vectored interrupt support in TLB exception handler generator.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-19 04:14:13 +02:00
Ralf Baechle
6fd11a2173 [MIPS] Cleanup free_initmem the same way as i386 did.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-04-19 04:14:12 +02:00
Dave Hansen
22a9835c35 [PATCH] unify PFN_* macros
Just about every architecture defines some macros to do operations on pfns.
 They're all virtually identical.  This patch consolidates all of them.

One minor glitch is that at least i386 uses them in a very skeletal header
file.  To keep away from #include dependency hell, I stuck the new
definitions in a new, isolated header.

Of all of the implementations, sh64 is the only one that varied by a bit.
It used some masks to ensure that any sign-extension got ripped away before
the arithmetic is done.  This has been posted to that sh64 maintainers and
the development list.

Compiles on x86, x86_64, ia64 and ppc64.

Signed-off-by: Dave Hansen <haveblue@us.ibm.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-03-27 08:44:48 -08:00
Alexey Dobriyan
53b3531bbb [PATCH] s/;;/;/g
Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-03-24 07:33:24 -08:00
Nick Piggin
7835e98b2e [PATCH] remove set_page_count() outside mm/
set_page_count usage outside mm/ is limited to setting the refcount to 1.
Remove set_page_count from outside mm/, and replace those users with
init_page_count() and set_page_refcounted().

This allows more debug checking, and tighter control on how code is allowed
to play around with page->_count.

Signed-off-by: Nick Piggin <npiggin@suse.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-03-22 07:54:02 -08:00
Nick Piggin
8dfcc9ba27 [PATCH] mm: split highorder pages
Have an explicit mm call to split higher order pages into individual pages.
 Should help to avoid bugs and be more explicit about the code's intention.

Signed-off-by: Nick Piggin <npiggin@suse.de>
Cc: Russell King <rmk@arm.linux.org.uk>
Cc: David Howells <dhowells@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Chris Zankel <chris@zankel.net>
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-03-22 07:53:57 -08:00
Atsushi Nemoto
de862b488e [MIPS] TX49XX has prefetch.
The TX49XX has the prefetch instruction.  It supports only Pref_Load
(hint 0).  Actually changes in this patch except for Kconfig are not
have any effects, I added these changes to prevent misuse of unsupported
hints.
    
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-03-21 13:27:47 +00:00
Thiemo Seufer
c6281edb1d [MIPS] Kill tlb-andes.c.
Basically identical to c-r4k.c, so maintaining one is really enough.
    
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-03-21 13:27:47 +00:00
Ralf Baechle
a3dddd560e [MIPS] War on whitespace: cleanup initial spaces followed by tabs.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-03-21 13:27:47 +00:00
Ralf Baechle
8145095cd8 [MIPS] Remove CONFIG_BUILD_ELF64.
This option is no longer usable with supported compilers.  It will be
replaced by usage of -msym32 in a separate patch.
    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-03-21 13:27:46 +00:00
Atsushi Nemoto
37caa934af [MIPS] sc-rm7k.c cleanup
Use blast_scache_range, blast_inv_scache_range for rm7k scache routine.
Output code should be logically same.
    
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-03-21 13:27:45 +00:00
Atsushi Nemoto
de62893bc0 [MIPS] local_r4k_flush_cache_page fix
If dcache_size != icache_size or dcache_size != scache_size, or
set-associative cache, icache/scache does not flushed properly.  Make
blast_?cache_page_indexed() masks its index value correctly.  Also,
use physical address for physically indexed pcache/scache.
    
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-03-18 16:59:27 +00:00
Ralf Baechle
1443e483e3 [MIPS] Scatter a bunch of __init over tlbex.c.
Found by make buildcheck.
    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-03-09 18:05:10 +00:00
Ralf Baechle
4debe4f963 [MIPS] Initialize S-cache function pointers even on S-cache-less CPUs.
When a CPU has no scache, the scache flushing functions currently
aren't getting initialized and the NULL pointer is eventually called
as a function.  Initialize the scache flushing functions as a noop
when there's no scache.
    
Initial patch by me and most of the debugging done by Martin Michlmayr.
    
Signed-off-by: Martin Michlmayr <tbm@cyrius.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-28 17:04:19 +00:00
Ralf Baechle
51939fbb79 [MIPS] Sibyte: #if CONFIG_* doesn't fly.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-21 16:58:23 +00:00
Atsushi Nemoto
41700e7399 [MIPS] Add protected_blast_icache_range, blast_icache_range, etc.
Add blast_xxx_range(), protected_blast_xxx_range() etc. for common
use.  They are built by __BUILD_BLAST_CACHE_RANGE().
Use protected_cache_op() macro for various protected_ routines.
Output code should be logically same.
    
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-14 19:13:24 +00:00
Daniel Jacobowitz
3d503753b4 [MIPS] Support /proc/kcore for MIPS
I'm pretty sure that the CKSEG0 bits are wrong, but I did need to
cover that region - because the SB-1 kernel links at 0xffffffff80100000
or so, disassembly and printing static variables don't work unless the
debugger can read that region.
    
Signed-off-by: Daniel Jacobowitz <dan@codesourcery.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-07 13:30:25 +00:00
Atsushi Nemoto
d4264f1839 [MIPS] Remove wrong __user tags.
This fixes sparse warnings 'dereference of noderef expression'.
    
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-02-07 13:30:25 +00:00
Ralf Baechle
e7958bb90d MIPS: Rename MIPS_CPU_ISA_M{32,64} -> MIPS_CPU_ISA_M{32,64}R1.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2006-01-10 13:39:06 +00:00
Hugh Dickins
68352e6ee3 [PATCH] mips: setup_zero_pages count 1
Page count should be initialized to 1 on each of the MIPS empty zero pages,
to avoid a bad_page warning whenever one of them is freed from all mappings.

Signed-off-by: Hugh Dickins <hugh@veritas.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-12-12 08:57:43 -08:00
Ralf Baechle
d981733aaf [MIPS] Use reset_page_mapcount to initialize empty_zero_page usage counter.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-12-01 11:05:13 +00:00
Hugh Dickins
872fec16d9 [PATCH] mm: init_mm without ptlock
First step in pushing down the page_table_lock.  init_mm.page_table_lock has
been used throughout the architectures (usually for ioremap): not to serialize
kernel address space allocation (that's usually vmlist_lock), but because
pud_alloc,pmd_alloc,pte_alloc_kernel expect caller holds it.

Reverse that: don't lock or unlock init_mm.page_table_lock in any of the
architectures; instead rely on pud_alloc,pmd_alloc,pte_alloc_kernel to take
and drop it when allocating a new one, to check lest a racing task already
did.  Similarly no page_table_lock in vmalloc's map_vm_area.

Some temporary ugliness in __pud_alloc and __pmd_alloc: since they also handle
user mms, which are converted only by a later patch, for now they have to lock
differently according to whether or not it's init_mm.

If sources get muddled, there's a danger that an arch source taking
init_mm.page_table_lock will be mixed with common source also taking it (or
neither take it).  So break the rules and make another change, which should
break the build for such a mismatch: remove the redundant mm arg from
pte_alloc_kernel (ppc64 scrapped its distinct ioremap_mm in 2.6.13).

Exceptions: arm26 used pte_alloc_kernel on user mm, now pte_alloc_map; ia64
used pte_alloc_map on init_mm, now pte_alloc_kernel; parisc had bad args to
pmd_alloc and pte_alloc_kernel in unused USE_HPPA_IOREMAP code; ppc64
map_io_page forgot to unlock on failure; ppc mmu_mapin_ram and ppc64 im_free
took page_table_lock for no good reason.

Signed-off-by: Hugh Dickins <hugh@veritas.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-10-29 21:40:40 -07:00
Andrew Isaacson
a4b5bd9abc SB1 cache exception handling.
Expand SB1 cache error handling by adding SB1_CEX_ALWAYS_FATAL and
SB1_CEX_STALL, allowing configurable behavior on cache errors.
    
Signed-Off-By: Andy Isaacson <adi@broadcom.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:32:48 +01:00
Andrew Isaacson
93ce2f524e Add support for SB1A CPU.
Signed-Off-By: Andy Isaacson <adi@broadcom.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:32:46 +01:00
Atsushi Nemoto
750ccf687f Fix zero length sys_cacheflush
Cacheflush(0, 0, 0) was crashing the system.  This is because
flush_icache_range(start, end) tries to flushing whole address space
(0 - ~0UL) if both start and end are zero.
    
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:32:44 +01:00
Ralf Baechle
6ec25809c1 Rename page argument of flush_cache_page to something more descriptive.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:32:42 +01:00
Ralf Baechle
dbc571690e Fix wrong comment.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:32:38 +01:00
Ralf Baechle
ec917c2c1a Fixup a few lose ends in explicit support for MIPS R1/R2.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:32:37 +01:00
Ralf Baechle
65f1f5a2c3 Don't copy SB1 cache error handler to uncached memory.
This may have made sense on a paranoid day with pass 1 BCM1250 processors
that were throwing cache error exception left and right for no good
reason.  On modern silicion that hardly makes sense and the code had
gotten just an obscurity ...
    
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:32:34 +01:00
Andrew Isaacson
46dc3a4a09 Fix stale comment in c-sb1.c.
Signed-Off-By: Andrew Isaacson <adi@broadcom.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:32:33 +01:00
Ralf Baechle
02cf211968 Cleanup the mess in cpu_cache_init.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:32:32 +01:00
Ralf Baechle
f5cfa980e5 Use R4000 TLB routines for SB1 also.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:32:31 +01:00
Atsushi Nemoto
9043f7e95d Sync c-tx39.c with c-r4k.c.
tx39_flush_cache_range() does nothing if !cpu_has_dc_aliases.  It should
flush d-cache and invalidate i-cache since the TX39(H2) has separate I/D
cache.
    
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:32:28 +01:00
Thiemo Seufer
10a3dabddd Add/Fix missing bit of R4600 hit cacheop workaround.
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:32:18 +01:00
Thiemo Seufer
02fe2c9ce3 Minor code cleanup.
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:32:17 +01:00
Thiemo Seufer
f5b4d9563b R4600 v2.0 needs a nop before tlbp.
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:32:17 +01:00
Thiemo Seufer
424cadae94 Don't set up a sg dma address if we have no page address for some reason.
Code cleanup.

Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:32:17 +01:00
Thiemo Seufer
d8748a3abf More .set push/pop.
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:32:16 +01:00
Thiemo Seufer
330cfe016b Let r4600 PRID detection match only legacy CPUs, cleanups.
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:32:15 +01:00
Ralf Baechle
7623debf26 Handle mtc0 - tlb write hazard for VR5432.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:32:12 +01:00
Ralf Baechle
1d40cfcd34 Avoid SMP cacheflushes. This is a minor optimization of startup but
will also avoid smp_call_function from doing stupid things when called
from a CPU that is not yet marked online.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:31:54 +01:00
Pete Popov
bdf21b18b4 Philips PNX8550 support: MIPS32-like core with 2 Trimedias on it.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:31:54 +01:00
Ralf Baechle
e01402b115 More AP / SP bits for the 34K, the Malta bits and things. Still wants
a little polishing.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:31:53 +01:00
Ralf Baechle
ec74e361f1 Mark a few variables __read_mostly.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:31:46 +01:00
Ralf Baechle
cc61c1fede MIPS R2 instruction hazard handling.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:31:46 +01:00
Ralf Baechle
bbc7f22f6d Detect the 34K.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:31:45 +01:00
Ralf Baechle
60080265a1 Define kmap_atomic_pfn() for MIPS.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:31:42 +01:00
Ralf Baechle
3ef33e68c1 Date: Fri Jul 8 20:10:17 2005 +0000
Those literals are long.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:31:40 +01:00
Ralf Baechle
6e760c8dae Rename CONFIG_CPU_MIPS{32,64} to CONFIG_CPU_MIPS{32|64}_R1.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:31:37 +01:00
Maciej W. Rozycki
2c93e12cfe Avoid tlbw* hazards for the R4600/R4700/R5000.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:31:34 +01:00
Maciej W. Rozycki
c3455b0efc Inline ioremap() calls for constant addresses that map to KSEG1.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:31:34 +01:00
Maciej W. Rozycki
4c0a2d4275 Fix the diagnostic dump for the XTLB refill handler.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:31:32 +01:00
Maciej W. Rozycki
41986a6e7e Fix a diagnostic message.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:31:32 +01:00
Maciej W. Rozycki
c6ad7b7d3c Use macros for the RM7k cp0.config bits instead of magic numbers.
Minor clean-ups.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:31:28 +01:00
Maciej W. Rozycki
fded2e508a Optimize R3k TLB Load/Store/Modified handlers, by scheduling
delay slots properly and avoiding an unnecessary jump to a jump.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:31:22 +01:00
Maciej W. Rozycki
d925c262dd Fill R3k load delay slots properly.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:31:21 +01:00
Maciej W. Rozycki
9678e28b1a Only dump instructions actually emitted.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:31:21 +01:00
Thiemo Seufer
63b2d2f4d2 Handle _PAGE_DIRTY correctly for CONFIG_64BIT_PHYS_ADDR on 32bit CPUs.
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:31:11 +01:00
Thiemo Seufer
ba5187dbb4 Better interface to run uncached cache setup code.
Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:31:11 +01:00
Ralf Baechle
1342f7e6c5 Arrested for multiple offences of header file inclusion.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:31:07 +01:00
Thiemo Seufer
172546bf60 Fix race conditions for read_c0_entryhi. Remove broken ASID masks in
tlb-sb1.c. Make tlb-r4k.c and tlb-sb1.c more similiar and more efficient.

Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:31:01 +01:00
Maciej W. Rozycki
202d0388e7 Remove useless casts. Fix formatting.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:31:00 +01:00
Thiemo Seufer
1b3a6e975c Fix 64bit SMP TLB handler and stack frame handling, optimize 32bit SMP
TLB handlers a bit, match definitions in pgtable-{32,64}.h better.

Signed-off-by: Thiemo Seufer <ths@networkno.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:31:00 +01:00
Ralf Baechle
6cbe063159 R4300 delay slot.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:30:59 +01:00
Ralf Baechle
53de0d471f Reformat; cosmetic cleanups.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:30:57 +01:00
Ralf Baechle
9ff77c469e Export shm_align_mask and flush_data_cache_page.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:30:54 +01:00
Ralf Baechle
77c728c224 Gcc 4.0 fixes.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:30:53 +01:00
Ralf Baechle
fe00f943e0 Sparseify MIPS.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2005-10-29 19:30:50 +01:00