Let's allow page-alignment in general for per-cpu data (wanted by Xen, and
Ingo suggested KVM as well).
Because larger alignments can use more room, we increase the max per-cpu
memory to 64k rather than 32k: it's getting a little tight.
Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
Signed-off-by: Jeremy Fitzhardinge <jeremy@xensource.com>
Signed-off-by: Andi Kleen <ak@suse.de>
Acked-by: Ingo Molnar <mingo@elte.hu>
Cc: Andi Kleen <ak@suse.de>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
PCI based SNI RM machines have their EISA bus behind an Intel PCI/EISA
bridge. So the PCI IO range must start at 0x0000. Changing that will
break the PCI bus, because i8259.c already has registered it's IO
addresses before the PCI bus gets initialized. Below is a patch,
which will register the PCI host bridge resources inside
register_pci_controller(). It also changes i8259.c to use insert_region(),
because request_resource() will fail, if the IO space of the PIT hanging
of the PCI host bridge (maybe passing the resource parent to
init_i8259_irqs() is a cleaner fix for that).
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
With commit 63dc68a8cf, kernel can not
handle BUG() and BUG_ON() properly since get_user() returns false for
kernel code. Use __get_user() to skip unnecessary access_ok(). This
patch also make BRK_BUG code encoded in the TNE instruction.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The save_fp_context()/restore_fp_context() might sleep on accessing
user stack and therefore might lose FPU ownership in middle of them.
If these function failed due to "in_atomic" test in do_page_fault,
touch the sigcontext area in non-atomic context and retry these
save/restore operation.
This is a replacement of a (broken) fix which was titled "Allow CpU
exception in kernel partially".
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
The commit 4d40bff7110e9e1a97ff8c01bdd6350e9867cc10 ("Allow CpU
exception in kernel partially") was broken. The commit was to fix
theoretical problem but broke usual case. Revert it for now.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
local_irq_restore -> raw_local_irq_restore -> irq_restore_epilog ->
smtc_ipi_replay -> smtc_ipi_dq -> spin_unlock_irqrestore ->
_spin_unlock_irqrestore -> local_irq_restore
The recursion does abort when there is no more IPI queued for a CPU, so
this isn't usually fatal which is why we got away with this for so long
until this was discovered by code inspection.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Make smtc_setup_irq() update the list of interrupts which need to be
watched by the debug code itself. Also there is no need to initialize the
IPI swint when running with a single VPE, so don't initialize it.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Between the mtc0 or di instruction that disables interrupts and the
following hazard barrier a processor may still take interrupts. If an
interrupt is taken after interrupts are disabled but before the state
is updated it will appear to restore_all that it is incorrectly returning
with interrupts disabled.
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Check the IEP bit for R3000 style processors when checking to see if
interrupts will be reenabled in restore_all.
Signed-off-by: Chris Dearman <chris@mips.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
RTLX communication is based on lock-free shared memory buffers. It
happened to be working by luck so far but relies on the optimizer doing
certain optimizations but no reordering.
Fixed by inserting proper barriers in rtlx_read and rtlx_write, and careful
pointer dereferencing.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Commit 6d6671066a is incomplete and misses
non-r4k CPUs. This patch reverts the commit and fixes in other way.
o Do FCSR checking in caller of restore_fp_context.
o Send SIGFPE if the signal handler set any FPU exception bits.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
IA64 and ARM-OABI are currently using their own version of epoll compat_
code.
An architecture needs epoll_event translation if alignof(u64) in 32 bit
mode is different from alignof(u64) in 64 bit mode. If an architecture
needs epoll_event translation, it must define struct compat_epoll_event in
asm/compat.h and set CONFIG_HAVE_COMPAT_EPOLL_EVENT and use
compat_sys_epoll_ctl and compat_sys_epoll_wait.
All 64 bit architecture should use compat_sys_epoll_pwait.
[sfr: restructure and move to fs/compat.c, remove MIPS version
of compat_sys_epoll_pwait, use __put_user_unaligned]
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: David Woodhouse <dwmw2@infradead.org>
Cc: Russell King <rmk@arm.linux.org.uk>
Cc: "Luck, Tony" <tony.luck@intel.com>
Cc: "David S. Miller" <davem@davemloft.net>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Many Makefiles in arch/mips have EXTRA_AFLAGS := $(CFLAGS) line. This
is redundant while AFLAGS contains $(cflags-y) and any options only
listed in CFLAGS (not in cflags-y) should be unnecessary for asm
sources.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This patch adds trivial support for SMARTMIPS extension. This extension
is currently implemented by 4KS[CD] CPUs.
Basically it saves/restores ACX register, which is part of the SMARTMIPS
ASE, when needed. This patch does *not* add any support for Smartmips MMU
features.
Futhermore this patch does not add explicit support for 4KS[CD] CPUs since
they are respectively mips32 and mips32r2 compliant. So with the current
processor configuration, a platform that has such CPUs needs to select
both configs:
CPU_HAS_SMARTMIPS
SYS_HAS_CPU_MIPS32_R[12]
This is due to the processor configuration which is mixing up all the
architecture variants and the processor types.
The drawback of this, is that we currently pass '-march=mips32' option to
gcc when building a kernel instead of '-march=4ksc' for 4KSC case. This
can lead to a kernel image a little bit bigger than required.
Signed-off-by: Franck Bui-Huu <fbuihuu@gmail.com>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
[NET] Eliminate user-selectable CONFIG_MV643XX_ETH_[012]
[MIPS] Drop __init from init_8259A()
[MIPS] Fix Kconfig typo bug
[MIPS] Fix double signal on trap and break instruction
[MIPS] sigset_32 has been made redundand by compat_sigset_t.
[MIPS] emma2rh: Remove needless <asm/i8259.h> inclusion.
[MIPS] Add MTD device support for Cobalt
init_8259A() is called from i8259A_resume() so should not be marked as
__init. And add some tests for whether 8259A was already initialized
or not.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit broke gdb, since any BREAK or TRAP instruction cause SIGSEGV.
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This fixes some sparse warnings. ("warning: symbol 'foo' was not
declared. Should it be static?")
Signed-off-by: Atsushi Nemoto <anemo@mba.ocn.ne.jp>
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus:
[MIPS] Update defconfigs
[MIPS] Support for several more SNI RM models.
[MIPS] Include <asm/bugs> to for declaration of check_bugs32.
[MIPS] Add external declaration of pagetable_init() to pgalloc.h
[MIPS] Make kernel_thread_helper() static
[MIPS] Make __declare_dbe_table static and avoid it getting optimized away
[MIPS] Use MIPS R2 instructions for bitops.
[MIPS] signals: Share even more code.
[MIPS] Fix CONFIG_MIPS32_N32=y CONFIG_MIPS32_O32=n build
[MIPS] Iomap implementation.
[MIPS] <asm/compat-signal.h> needs to include <asm/uaccess.h>.
[MIPS] IP27: Fix warning.
[MIPS] Fix sigset_t endianess swapping issues in 32-bit compat code.
