This adds preliminary support for the SH7786 CPU subtype.
While this is a dual-core CPU, only UP is supported for now. L2 cache
support is likewise not yet implemented.
More information on this particular CPU subtype is available at:
http://www.renesas.com/fmwk.jsp?cnt=sh7786_root.jsp&fp=/products/mpumcu/superh_family/sh7780_series/sh7786_group/
Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
With the recent entry.S refactoring, the SH-X3 path had a mov.l for a
register to register copy, resulting in:
AS arch/sh/kernel/cpu/sh4/../sh3/entry.o
arch/sh/kernel/cpu/sh4/../sh3/entry.S: Assembler messages:
arch/sh/kernel/cpu/sh4/../sh3/entry.S:366: Error: invalid operands for opcode
make[3]: *** [arch/sh/kernel/cpu/sh4/../sh3/entry.o] Error 1
Switch it over to a mov to fix it up.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Update intc tables and platform data to use one linux irq
per maskable interrupt source instead of keeping the one-to-one
mapping between vectors and linux irqs.
This fixes potential irq masking issues for sh7785 hardware
blocks such as SCIF/DMAC/PCIC5/MMCIF/GDTA/FLCTL/GPIO
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Tested-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Update intc tables and platform data to use one linux irq
per maskable interrupt source instead of keeping the one-to-one
mapping between vectors and linux irqs.
This fixes potential irq masking issues for sh7780 hardware
blocks such as SCIF/RTC/DMAC/PCIC5/MMCIF/FLCTL/GPIO
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Update intc tables and platform data to use one linux irq
per maskable interrupt source instead of keeping the one-to-one
mapping between vectors and linux irqs.
This fixes potential irq masking issues for sh775x hardware
blocks such as SCI/SCIF/RTC/DMAC/TMU2/REF.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Instead of keeping the single vector -> single linux irq mapping
we extend the intc code to support merging of vectors to a single
linux irq. This helps processors such as sh7750, sh7780 and sh7785
which have more vectors than masking ability. With this patch in
place we can modify the intc tables to use one irq per maskable
irq source. Please note the following:
- If multiple vectors share the same enum then only the
first vector will be available as a linux irq.
- Drivers may need to be rewritten to get pending irq
source from the hardware block instead of irq number.
This patch together with the sh7785 specific intc tables solves
DMA controller irq issues related to buggy interrupt masking.
Reported-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Prefetch early exception data. There is unused space in our
exception handler cache line anyway, so this is almost free.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Remove EXPEVT vector from the stack, lookup_exception_vector()
for sh3/sh4/sh4a is already using k2 to get the vector.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch reworks the sh3/sh4/sh4a register restore code in
the following ways:
- break out restore_regs() from restore_all()
- the register saving order is unchanged
- use restore_regs() in sh_bios_handler and restore_all
- document the function
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch reworks the sh3/sh4/sh4a register saving code in
the following ways:
- break out prepare_stack_save_dsp() from handle_exception()
- break out save_regs() from handle_exception()
- the register saving order is unchanged
- align new functions to fit in cache lines
- separate exception code from interrupt code
- keep main code flow in a single cache line per exception vector
- use bsr/rts for regular functions (save pr first)
- keep data in one shared cache line (exception_data)
- document the functions
- tie in the hp6xx code
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
The C99 specification states in section 6.11.5:
The placement of a storage-class specifier other than at the
beginning of the declaration specifiers in a declaration is an
obsolescent feature.
Signed-off-by: Tobias Klauser <tklauser@distanz.ch>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
GENERIC_TIME still depends on the clocksource bits being there, which is
presently not supported. This allows the CMT clockevent driver to be used
alongside alternate system timers that do not yet provide a clocksource
of their own (MTU2 and so on in the case of SH-2A).
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
CMT platform data for SuperH Mobile sh7723/sh7722/sh7343/sh7366.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Add TMU disable support so we can use other clockevents.
Also, setup the clockevent rating.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Rework and simplify the sched_clock and clocksource code. Instead
of registering the clocksource in a shared file we move it into the
tmu driver. Also, add code to handle sched_clock in the case of no
clocksource.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
The T-bit manipulation for syscall error checking had the side effect of
spuriously returning ERESTART* errno values over EINTR. So, we simplify
the error checking a bit and leave the T-bit alone.
Reported-by: Kaz Kojima <kkojima@rr.iij4u.or.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This fixes a bug in the FPU exception handler for the FCNVDS instruction.
To get the register number the instruction is shifted right by 9,
though it should be shifted right by 8.
More information at ST Linux bugzilla:
https://bugzilla.stlinux.com/show_bug.cgi?id=4892
Signed-off-by: Giuseppe Di Giore <giuseppe.di-giore@st.com>
Signed-off-by: Carmelo Amoroso <carmelo.amoroso@st.com>
Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
CPUs define pinmux tables through the optional interface, while boards
that require demux of their own require it explicitly. Roll the Makefile
rules back to depend on GENERIC_GPIO, which covers both cases.
Fixes a link error with an undefined reference to register_pinmux() on
optional platforms.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch updates the SuperH gpio code to make use of gpiolib. The
gpiolib callbacks get() and set() are lockless, but we use our own
spinlock for the other operations to make sure hardware register
bitfield accesses stay atomic.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch optimizes the gpio data register handling for gpio_set_value().
Instead of using the good old spinlock-plus-read-modify-write strategy
we now use a shadow register and atomic operations.
This improves the bitbanging mmc performance on Migo-R from 26 Kbytes/s
to 40 Kbytes/s.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch separates the register read and write functions to
allow lockless gpio_get_value().
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch modifies the table based SuperH gpio implementation to
make use of direct table lookups. With this change the functions
gpio_get_value() and gpio_set_value() are O(1).
Tested on Migo-R using bitbanging mmc. Performance is improved from
11 KBytes/s to 26 Kbytes/s.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
unaligned and nonexistent address causes wrong exception
handling in traps_32.c(handle_unaligned_access).
'handle_unalinged_ins' should return -EFAULT if address error
is fixed up with kernel exception table, otherwise
'handle_unaligned_access' increases already fixed program counter
and then crash.
for example
ioctl(fd, TCGETA, (struct termio *)-1)
never return and stay in TASK_UNINTERRUPTIBLE state forever
in my kernel.
Signed-off-by: SUGIOKA Toshinobu <sugioka@itonet.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch exports the sh7343 JPU to user space using uio_pdrv_genirq,
very similar to the sh7722 JPU patch by Hayama-san.
While at it fix up the end of the sh7722 JPU iomem resource.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Remove __attribute__((weak)) from common code sys_pipe implemantation.
IA64, ALPHA, SUPERH (32bit) and SPARC (32bit) have own implemantations
with the same name. Just rename them.
For sys_pipe2 there is no architecture specific implementation.
Cc: Richard Henderson <rth@twiddle.net>
Cc: David S. Miller <davem@davemloft.net>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: Tony Luck <tony.luck@intel.com>
Signed-off-by: Heiko Carstens <heiko.carstens@de.ibm.com>
Impact: build fix
Ingo Molnar wrote:
> tip/arch/blackfin/kernel/irqchip.c: In function 'show_interrupts':
> tip/arch/blackfin/kernel/irqchip.c:85: error: 'struct kernel_stat' has no member named 'irqs'
> make[2]: *** [arch/blackfin/kernel/irqchip.o] Error 1
> make[2]: *** Waiting for unfinished jobs....
>
So could move kstat_irqs array to irq_desc struct.
(s390, m68k, sparc) are not touched yet, because they don't support genirq
Signed-off-by: Yinghai Lu <yinghai@kernel.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
While looking at reducing the amount of architecture namespace pollution
in the generic kernel, I found that asm/irq.h is included in the vast
majority of compilations on ARM (around 650 files.)
Since asm/irq.h includes a sub-architecture include file on ARM, this
causes a negative impact on the ccache's ability to re-use the build
results from other sub-architectures, so we have a desire to reduce the
dependencies on asm/irq.h.
It turns out that a major cause of this is the needless include of
linux/hardirq.h into asm-generic/local.h. The patch below removes this
include, resulting in some 250 to 300 files (around half) of the kernel
then omitting asm/irq.h.
My test builds still succeed, provided two ARM files are fixed
(arch/arm/kernel/traps.c and arch/arm/mm/fault.c) - so there may be
negative impacts for this on other architectures.
Note that x86 does not include asm/irq.h nor linux/hardirq.h in its
asm/local.h, so this patch can be viewed as bringing the generic version
into line with the x86 version.
[kosaki.motohiro@jp.fujitsu.com: add #include <linux/irqflags.h> to acpi/processor_idle.c]
[adobriyan@gmail.com: fix sparc64]
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: KOSAKI Motohiro <kosaki.motohiro@jp.fujitsu.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Alexey Dobriyan <adobriyan@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* 'cpus4096-for-linus-2' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (66 commits)
x86: export vector_used_by_percpu_irq
x86: use logical apicid in x2apic_cluster's x2apic_cpu_mask_to_apicid_and()
sched: nominate preferred wakeup cpu, fix
x86: fix lguest used_vectors breakage, -v2
x86: fix warning in arch/x86/kernel/io_apic.c
sched: fix warning in kernel/sched.c
sched: move test_sd_parent() to an SMP section of sched.h
sched: add SD_BALANCE_NEWIDLE at MC and CPU level for sched_mc>0
sched: activate active load balancing in new idle cpus
sched: bias task wakeups to preferred semi-idle packages
sched: nominate preferred wakeup cpu
sched: favour lower logical cpu number for sched_mc balance
sched: framework for sched_mc/smt_power_savings=N
sched: convert BALANCE_FOR_xx_POWER to inline functions
x86: use possible_cpus=NUM to extend the possible cpus allowed
x86: fix cpu_mask_to_apicid_and to include cpu_online_mask
x86: update io_apic.c to the new cpumask code
x86: Introduce topology_core_cpumask()/topology_thread_cpumask()
x86: xen: use smp_call_function_many()
x86: use work_on_cpu in x86/kernel/cpu/mcheck/mce_amd_64.c
...
Fixed up trivial conflict in kernel/time/tick-sched.c manually
arch_setup_additional_pages currently gets two arguments, the binary
format descripton and an indication if the process uses an executable
stack or not. The second argument is not used by anybody, it could
be removed without replacement.
What actually does make sense is to pass an indication if the process
uses the elf interpreter or not. The glibc code will not use anything
from the vdso if the process does not use the dynamic linker, so for
statically linked binaries the architecture backend can choose not
to map the vdso.
Acked-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Martin Schwidefsky <schwidefsky@de.ibm.com>
Add JPU support on Migo-R via UIO. This make use of Magnus's
generic UIO platform driver. Chunk of contiguous memory to hold
intermediate image and compressed data during encode and decode.
Signed-off-by: Takanari Hayama <taki@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
We don't really want this enabled by default, but it is still quite
useful for debugging. So, make it conditional and leave it off by
default.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This enables the same functionality that sh64 has for sh32. When running
on simulated hardware or via remote memory via the debug interface,
memory is gauranteed to be zero on boot already, and skipping the zeroing
of BSS has measurable boot time benefits.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Now that the rest of the boards that were using cf-enabler "generically"
have switched to setting up their mappings on their own, only the mach-se
boards were left using it. All of the cf-enabler using mach-se boards
use a special initialization of the MRSHPC windows rather than going
through the special PTE as other SH-4 platforms do. This consolidates
the MRSHPC setup logic, hooks it up on the boards that care, and gets rid
of any and all remaining references to cf-enabler.
This has been long overdue, as cf-enabler has been the bane of
arch/sh/kernel for the last 7 years. Good riddance.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This can use the same implementation as sh64, the generated assembly is
the same between the new and old version, so there is not much point in
leaving it open coded in inline assembly.
This is preparatory work for future consolidation of the _32/_64
variants.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Nothing is using this any more, so get rid of it before anyone gets the
bright idea to start using it again.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
With the reworked kgdb support, we always detach and reinitialize the
stub. This was mostly a feature for handoffs between sh-ipl+g and the
kgdb stub, but virtually no sh-ipl+g versions ever had this working
right in the first place.
Given that the sh-ipl+g stubs in general use today don't even support
the GDB stub, and we have already killed off the special casing in the
sh-sci serial driver, kill off this now unused symbol too.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This migrates from the old bitrotted kgdb stub implementation and moves
to the generic stub. In the process support for SH-2/SH-2A is also added,
which the old stub never provided.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Presently these cases are not handled properly due to the return value
not being passed back. This needs to be correct to get proper behaviour
out of things like the tracehook signal notifier, amongst others.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This converts the sh64 /proc/asids entry to debugfs and enables it for
all SH parts that have debugfs enabled.
On MMU systems this can be used to determine which processes are using
which ASIDs which in turn can be used for finer grained cache tag
analysis.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
These were left over from some time ago, sh64 never got around to
defining __HAVE_ARCH_TASK_STRUCT_ALLOCATOR during the conversion, and it
has no need to. Kill these off and use the generic versions instead.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
The INTEVT read at interrupt exception entry is uneccessary, as the read
is deferred until we are ready to enter do_IRQ(). The kgdb nmi path still
requires it, so move it there.
Signed-off-by: Aoi Shinkai <shinkoi2005@gmail.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Move the not-so-generic pm code from arch/sh/kernel/pm.c to the
platform directory together with the rest of the hp6xx pm code.
This is done to let non-hp6xx platforms enable CONFIG_PM.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Fix interrupt values for the first sh7343 SCIF port and
update the configuration to include the remaining 3 ones.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Make sure the 32 KHz r_clk rate gets propagated correctly. Without
this fix the clocks for RTC, CMT, KEYSC and RWDT are stuck at 0 Hz.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch adds support for the SH-2A FPU based SH7201 processor subtype.
Signed-off-by: Peter Griffin <pgriffin@mpc-data.co.uk>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Description snipped from Steven Rostedt's PPC patch:
When idle is called, interrupts are blocked, but the idle
function will still wake up on an interrupt. The problem is
that the interrupt disabled latency tracer will take this call
to idle as a latency.
This patch disables the latency tracing when going into idle.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This implements a simple show_code() that is in turn plugged in to
show_regs() to provide minimal code dumping at the end of the trace.
Built on top of a simple instruction disassembler derived from the
binutils opcode table.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This moves in the necessary libgcc bits for SUPERH32 and drops the
libgcc linking for the regular targets. This in turn allows us to rip
out quite a few hacks both in sh_ksyms_32 and arch/sh/Makefile.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
CC arch/sh/kernel/cpu/clock.o
arch/sh/kernel/cpu/clock.c: In function 'clk_disable':
arch/sh/kernel/cpu/clock.c:156: warning: 'return' with a value, in function returning void
Introduced by ("sh: enable and disable clocks recursively").
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Add clock framework support to the usb/r8a66597 driver and
adjust the cpu specific code accordingly.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Add clock framework support to the usbf/m66592 driver and
adjust the cpu specific code accordingly.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Add clock framework support to the sh_mobile i2c driver and
adjust the processor specific code accordingly.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Add sh7366 mstpcr bits and information about their parent clocks.
The datasheet is pretty clear about the clocks on this device.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Add sh7343 mstpcr bits and information about their parent clocks.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Add sh7723 mstpcr bits and information about their parent clocks.
The datasheet is pretty clear about the clocks on this device.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Add sh7722 mstpcr bits and information about their parent clocks.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Add base code to handle new mstpcr clocks. Make sure clock rates propagate.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Impact: change calling convention of existing clock_event APIs
struct clock_event_timer's cpumask field gets changed to take pointer,
as does the ->broadcast function.
Another single-patch change. For safety, we BUG_ON() in
clockevents_register_device() if it's not set.
Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
Cc: Ingo Molnar <mingo@elte.hu>
Impact: cleanup
Each SMP arch defines these themselves. Move them to a central
location.
Twists:
1) Some archs (m32, parisc, s390) set possible_map to all 1, so we add a
CONFIG_INIT_ALL_POSSIBLE for this rather than break them.
2) mips and sparc32 '#define cpu_possible_map phys_cpu_present_map'.
Those archs simply have phys_cpu_present_map replaced everywhere.
3) Alpha defined cpu_possible_map to cpu_present_map; this is tricky
so I just manipulate them both in sync.
4) IA64, cris and m32r have gratuitous 'extern cpumask_t cpu_possible_map'
declarations.
Signed-off-by: Rusty Russell <rusty@rustcorp.com.au>
Reviewed-by: Grant Grundler <grundler@parisc-linux.org>
Tested-by: Tony Luck <tony.luck@intel.com>
Acked-by: Ingo Molnar <mingo@elte.hu>
Cc: Mike Travis <travis@sgi.com>
Cc: ink@jurassic.park.msu.ru
Cc: rmk@arm.linux.org.uk
Cc: starvik@axis.com
Cc: tony.luck@intel.com
Cc: takata@linux-m32r.org
Cc: ralf@linux-mips.org
Cc: grundler@parisc-linux.org
Cc: paulus@samba.org
Cc: schwidefsky@de.ibm.com
Cc: lethal@linux-sh.org
Cc: wli@holomorphy.com
Cc: davem@davemloft.net
Cc: jdike@addtoit.com
Cc: mingo@redhat.com
Under qemu there is a race between the TDxE read-and-clear and the SCxTDR
write. While on hardware it can be gauranteed that the read-and-clear
will happen prior to the character being written out, no such assumption
can be made under emulation. As this path happens with IRQs off and the
hardware itself doesn't care about the ordering, move the SCxTDR write
until after the read-and-clear.
Signed-off-by: Vladimir Prus <vladimir@codesourcery.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch fixes the TMU0 interrupt frequency on suspend/resume.
During the resume the kernel reprograms the TMU0.ClockEvent mode
but if the mode is periodic than the TMU0.TCOR is updated with
a random wrong value without taking care latest valid saved value.
There was no problem with No_HZ system where TMU0.TCOR isn't used.
Signed-off-by: Francesco M. Virlinzi <francesco.virlinzi@st.com>
Signed-off-by: Stuart Menefy <stuart.menefy@st.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch changes sci type of SH7723 from PORT_SCI to PORT_SCIFA.
Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch add usb setting for sh 7366
Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Presently there is very little standing in the way of using an SH-4
toolchain for building an SH-2 kernel, and vice versa. Binutils itself
has no limitations whatsoever and supports explicit ISA hinting, which
we already use with varying degrees of success today.
This leaves GCC as the odd one out, due to a rather dubious policy
decision by the GCC folks to not include all of the CPU family variants
in the default list of multilib targets in GCC4. Despite best efforts to
the contrary, libgcc itself already contains awareness of the various CPU
types and remains generally usable, allowing it to safely be referenced
even on a mismatched target (and indeed, explicit ISA tuning by binutils
keeps us honest in terms of ensuring that we do not link incompatible
objects in).
In order to support this, a couple of changes had to be made. Firstly,
the introduction of MAYBE_DECLARE_EXPORT(), which provides a __weak
extern reference for libgcc resident routines when finer-grained
-m<cpu-family> based tuning is not supported by the toolchain. This
fixes up the __sdivsi3_i4i and __udivsi3_i4i references when dealing
with SH-2 kernels linked with an SH-4 libgcc. Secondly, in case where we
are unable to find a suitable match for CPU family tuning but still
have a toolchain that defaults to FP instruction generation, a suitable
nofpu target must be selected. This is accomplished by selecting the
first nofpu multilib target supported by the toolchain, which is
also necessary for selecting the proper libgcc to link against.
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch implements pinmux tables for the sh7785 processor.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This patch improves the support for gpio pins that are hard wired
to either input or output and lack control register association.
A special force enum id is used to allow use without control
register but still mark the gpio pin as input or output.
Signed-off-by: Magnus Damm <damm@igel.co.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
