Commit Graph

315 Commits

Author SHA1 Message Date
Catalin Marinas
953233dc99 [ARM] 4134/1: Add generic support for outer caches
The outer cache can be L2 as on RealView/EB MPCore platform or even L3
or further on ARMv7 cores. This patch adds the generic support for
flushing the outer cache in the DMA operations.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-02-08 14:49:40 +00:00
Catalin Marinas
e6a5d66f58 [ARM] 4129/1: Add barriers after the TLB operations
The architecture specification states that TLB operations are
guaranteed to be complete only after the execution of a DSB (Data
Synchronisation Barrier, former Data Write Barrier or Drain Write
Buffer). The branch target cache invalidation is also needed. The ISB
(Instruction Synchronisation Barrier, formerly Prefetch Flush) is
needed unless there will be a return from exception before the
corresponding mapping is used (i.e. user mappings).

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-02-08 14:49:27 +00:00
Catalin Marinas
9d99df4b10 [ARM] 4128/1: Architecture compliant TTBR changing sequence
On newer architectures (ARMv6, ARMv7), the depth of the prefetch and
branch prediction is implementation defined and there is a small risk
of wrong ASID tagging when changing TTBR0 before setting the new
context id. The recommended solution is to set a reserved ASID during
TTBR changing. This patch reserves ASID 0.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-02-08 14:49:24 +00:00
Lennert Buytenhek
850b42933e [ARM] 4123/1: xsc3: general cleanup
This patch cleans up proc-xsc3:
- Correct a number of typos.
- Fix up indentation in a number of places.
- Change references to the various caches to be more clear about
  whether we're talking about the L1 D, the L1 I or the unified L2
  cache.
- Rename "drain write buffer" to "data write barrier", the official
  name used in the Manzano manual.
- Change the xsc3 cpu name from "XScale-Core3" to "XScale-V3 based
  processor".

Also, since a previously merged patch implements proper support for
using a MAC or iWMMXt coprocessor on xsc3 platforms, we no longer
need to enable access to CP0 on boot.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-02-08 14:48:44 +00:00
Catalin Marinas
412489af76 [ARM] 4112/1: Only ioremap to supersections if DOMAIN_IO is zero
Supersections do not have a field for the domain and it is always
0. This patch prevents the creation of supersections during ioremap
when DOMAIN_IO is not zero (i.e. !defined(CONFIG_IO_36)).

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-01-25 16:35:26 +00:00
Dan Williams
7f215abc69 [ARM] 4100/1: iop3xx: fix cpu mask for iop333
cosmetic fix so iop333 is not reported as ixp46x
iop333 cpuid = 0x69054210

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-01-24 11:59:57 +00:00
Russell King
204ecae4e1 [ARM] Fix show_mem() for discontigmem
show_mem() was assuming incorrectly that the mem_map for any
node started at PFN 0.  This is obviously wrong; fix it to
take account of node_start_pfn.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-01-24 11:59:56 +00:00
Russell King
6020dff092 [ARM] Resolve fuse and direct-IO failures due to missing cache flushes
fuse does not work on ARM due to cache incoherency issues - fuse wants
to use get_user_pages() to copy data from the current process into
kernel space.  However, since this accesses userspace via the kernel
mapping, the kernel mapping can be out of date wrt data written to
userspace.

This can lead to unpredictable behaviour (in the case of fuse) or data
corruption for direct-IO.

This resolves debian bug #402876

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2007-01-08 19:49:58 +00:00
Richard Purdie
1c9d3df5e8 [ARM] 4078/1: Fix ARM copypage cache coherency problems
If PG_dcache_dirty is set for a page, we need to flush the source page
before performing any copypage operation using a different virtual address.

This fixes the copypage implementations for XScale, StrongARM and ARMv6.

This patch fixes segmentation faults seen in the dynamic linker under
the usage patterns in glibc 2.4/2.5.

Signed-off-by: Richard Purdie <rpurdie@rpsys.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-30 17:05:08 +00:00
Lennert Buytenhek
57fee39f44 [ARM] 4061/1: xsc3: change of maintainer
Deepak Saxena has agreed to hand xsc3 maintainership over to me.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-19 21:04:35 +00:00
Russell King
255d1f8639 [ARM] Fix warnings from asm/system.h
Move adjust_cr() into arch/arm/mm/mmu.c, and move irqflags.h to
a more appropriate place in the header file.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-18 00:12:47 +00:00
Russell King
c924aff853 [ARM] Fix BUG()s in ioremap() code
We need to ensure that the area size is page aligned so that
remap_area_pte() doesn't increment the address past the end of
the desired area.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-17 23:29:57 +00:00
Russell King
da2c12a279 [ARM] Clean up ioremap code
Since we're keeping the ioremap code, we might as well keep it as
close to the standard kernel as possible.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-13 14:35:58 +00:00
Russell King
ad1ae2fe7f [ARM] Unuse another Linux PTE bit
L_PTE_ASID is not really required to be stored in every PTE, since we
can identify it via the address passed to set_pte_at().  So, create
set_pte_ext() which takes the address of the PTE to set, the Linux
PTE value, and the additional CPU PTE bits which aren't encoded in
the Linux PTE value.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-13 14:34:43 +00:00
Russell King
94b1e96d9d [ARM] Formalise the ARMv6 processor name string
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-08 16:05:52 +00:00
Russell King
efe90d273b [ARM] Handle HWCAP_VFP in VFP support code
Don't set HWCAP_VFP in the processor support file; not only does it
depend on the processor features, but it also depends on the support
code being present.  Therefore, only set it if the support code
detects that we have a VFP coprocessor attached.

Also, move the VFP handling of the coprocessor access register into
the VFP support code.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-08 16:05:26 +00:00
Linus Torvalds
ea14fad0d4 Merge branch 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'for-linus' of master.kernel.org:/home/rmk/linux-2.6-arm: (76 commits)
  [ARM] 4002/1: S3C24XX: leave parent IRQs unmasked
  [ARM] 4001/1: S3C24XX: shorten reboot time
  [ARM] 3983/2: remove unused argument to __bug()
  [ARM] 4000/1: Osiris: add third serial port in
  [ARM] 3999/1: RX3715: suspend to RAM support
  [ARM] 3998/1: VR1000: LED platform devices
  [ARM] 3995/1: iop13xx: add iop13xx support
  [ARM] 3968/1: iop13xx: add iop13xx_defconfig
  [ARM] Update mach-types
  [ARM] Allow gcc to optimise arm_add_memory a little more
  [ARM] 3991/1: i.MX/MX1 high resolution time source
  [ARM] 3990/1: i.MX/MX1 more precise PLL decode
  [ARM] 3986/1: H1940: suspend to RAM support
  [ARM] 3985/1: ixp4xx clocksource cleanup
  [ARM] 3984/1: ixp4xx/nslu2: Fix disk LED numbering (take 2)
  [ARM] 3994/1: ixp23xx: fix handling of pci master aborts
  [ARM] 3981/1: sched_clock for PXA2xx
  [ARM] 3980/1: extend the ARM Versatile sched_clock implementation from 32 to 63 bit
  [ARM] 3979/1: extend the SA11x0 sched_clock implementation from 32 to 63 bit period
  [ARM] 3978/1: macro to provide a 63-bit value from a 32-bit hardware counter
  ...
2006-12-07 15:40:39 -08:00
Russell King
6705cda24f [ARM] Merge individual ARM sub-trees
Merge:
 Atmel AT91RM9200 and AT91SAM9260 changes
 General ARM developments
 Disconfiguous memory cleanups
 64-bit/32-bit division and sched_clock extension patches
 EP93xx support changes
 IOP support changes

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-07 23:07:26 +00:00
Ben Dooks
bbf6f2809d [ARM] 3999/1: RX3715: suspend to RAM support
The RX3715 is similar to the H1940 in the way
that suspend to RAM works, so we can use most
of the extant support for the H1940 with only
a few modifictions

Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-07 22:37:44 +00:00
Dan Williams
285f5fa7e9 [ARM] 3995/1: iop13xx: add iop13xx support
The iop348 processor integrates an Xscale (XSC3 512KB L2 Cache) core with a
Serial Attached SCSI (SAS) controller, multi-ported DDR2 memory
controller, 3 Application Direct Memory Access (DMA) controllers, a 133Mhz
PCI-X interface, a x8 PCI-Express interface, and other peripherals to form
a system-on-a-chip RAID subsystem engine.

The iop342 processor replaces the SAS controller with a second Xscale core
for dual core embedded applications.

The iop341 processor is the single core version of iop342.

This patch supports the two Intel customer reference platforms iq81340mc
for external storage and iq81340sc for direct attach (HBA) development.

The developer's manual is available here:
ftp://download.intel.com/design/iio/docs/31503701.pdf

Changelog:
* removed virtual addresses from resource definitions
* cleaned up some unnecessary #include's

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-07 17:20:21 +00:00
Peter Zijlstra
6edaf68a87 [PATCH] mm: arch do_page_fault() vs in_atomic()
In light of the recent pagefault and filemap_copy_from_user work I've gone
through all the arch pagefault handlers to make sure the inc_preempt_count()
'feature' works as expected.

Several sections of code (including the new filemap_copy_from_user) rely on
the fact that faults do not take locks under increased preempt count.

arch/x86_64 - good
arch/powerpc - good
arch/cris - fixed
arch/i386 - good
arch/parisc - fixed
arch/sh - good
arch/sparc - good
arch/s390 - good
arch/m68k - fixed
arch/ppc - good
arch/alpha - fixed
arch/mips - good
arch/sparc64 - good
arch/ia64 - good
arch/arm - fixed
arch/um - good
arch/avr32 - good
arch/h8300 - NA
arch/m32r - good
arch/v850 - good
arch/frv - fixed
arch/m68knommu - NA
arch/arm26 - fixed
arch/sh64 - fixed
arch/xtensa - good

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Acked-by: Nick Piggin <npiggin@suse.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-12-07 08:39:21 -08:00
Ben Dooks
9073341c2b [ARM] 3986/1: H1940: suspend to RAM support
Add support to suspend and resume, using the
H1940's bootloader

Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Arnaud Patard <arnaud.patard@rtp-net.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-07 16:17:49 +00:00
Lennert Buytenhek
afe4b25e7d [ARM] 3881/4: xscale: clean up cp0/cp1 handling
XScale cores either have a DSP coprocessor (which contains a single
40 bit accumulator register), or an iWMMXt coprocessor (which contains
eight 64 bit registers.)

Because of the small amount of state in the DSP coprocessor, access to
the DSP coprocessor (CP0) is always enabled, and DSP context switching
is done unconditionally on every task switch.  Access to the iWMMXt
coprocessor (CP0/CP1) is enabled only when an iWMMXt instruction is
first issued, and iWMMXt context switching is done lazily.

CONFIG_IWMMXT is supposed to mean 'the cpu we will be running on will
have iWMMXt support', but boards are supposed to select this config
symbol by hand, and at least one pxa27x board doesn't get this right,
so on that board, proc-xscale.S will incorrectly assume that we have a
DSP coprocessor, enable CP0 on boot, and we will then only save the
first iWMMXt register (wR0) on context switches, which is Bad.

This patch redefines CONFIG_IWMMXT as 'the cpu we will be running on
might have iWMMXt support, and we will enable iWMMXt context switching
if it does.'  This means that with this patch, running a CONFIG_IWMMXT=n
kernel on an iWMMXt-capable CPU will no longer potentially corrupt iWMMXt
state over context switches, and running a CONFIG_IWMMXT=y kernel on a
non-iWMMXt capable CPU will still do DSP context save/restore.

These changes should make iWMMXt work on PXA3xx, and as a side effect,
enable proper acc0 save/restore on non-iWMMXt capable xsc3 cores such
as IOP13xx and IXP23xx (which will not have CONFIG_CPU_XSCALE defined),
as well as setting and using HWCAP_IWMMXT properly.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Acked-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-03 17:52:22 +00:00
Dan Williams
f5236225a3 [ARM] 3967/1: xsc3: make branch predication configurable on xsc3
Remove BTB_ENABLE from proc-xsc3.S

On some early revisions of xsc3 enabling the branch target buffer can cause
crashes, see erratum #42.

Cc: Lennert Buytenhek <buytenh@wantstofly.org>

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-01 23:40:37 +00:00
Lennert Buytenhek
0e5fdca762 [ARM] 3971/1: xsc3: get rid of L_PTE_COHERENT
Merge L_PTE_COHERENT with L_PTE_SHARED and free up a L_PTE_* bit.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-12-01 23:40:23 +00:00
Russell King
3ff1559eae [ARM] Fix nommu build
Fix warnings and errors in arch/arm/mm for nommu build.
Remove commented out function prototype in pgtable-nommu.h

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-11-30 13:53:54 +00:00
Russell King
ee90dabcad [ARM] Include asm/elf.h instead of asm/procinfo.h
These files want to provide/access ELF hwcap information, so should
be including asm/elf.h rather than asm/procinfo.h

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-11-30 12:24:46 +00:00
Matt LaPlante
3cb2fccc5f Fix misc Kconfig typos
Fix various Kconfig typos.

Signed-off-by: Matt LaPlante <kernel1@cyberdogtech.com>
Acked-by: Randy Dunlap <randy.dunlap@oracle.com>
Signed-off-by: Adrian Bunk <bunk@stusta.de>
2006-11-30 05:22:59 +01:00
Dan Williams
105ef9a0af [ARM] 3942/1: ARM: comment: consistent_sync should not be called directly
/*
 * Note: Drivers should NOT use this function directly, as it will break
 * platforms with CONFIG_DMABOUNCE.
 * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
 */

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-11-22 22:45:57 +00:00
Ray Lehtiniemi
5e70982750 [ARM] 3927/1: Allow show_mem() to work with holes in memory map.
show_mem() was not correctly handling holes in the memory
map.  It was treating the freed sections of the map as
though they contained valid struct page entries.  This
could cause incorrect debugging output or even a kernel
panic.

This patch keeps the struct meminfo around after system
initialization so that show_mem() can use it when
scanning memory.  show_mem() now walks over each bank
of each online node, rather than assuming that each node
contains a single contiguous bank.

Signed-off-by: Ray Lehtiniemi <rayl@mail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-11-07 19:39:00 +00:00
Paul Gortmaker
8f7f9435e6 [ARM] 3912/1: Make PXA270 advertise HWCAP_IWMMXT capability
ARM patch 3756/1 added HWCAP_IWMMXT.  This patch adds support
for broadcasting that info via /proc/cpuinfo and sets it for
the CPU features of the PXA270.

I've booted 19rc3 on a pxa270 and confirmed that the /proc/cpuinfo
shows "iwmmxt" in the Features.

Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-11-02 22:58:53 +00:00
Al Viro
1622605cf6 [PATCH] arm: it's OK to pass pointer to volatile as iounmap() argument...
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-10-08 18:50:58 -07:00
Linus Torvalds
63c422afe3 Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm:
  [ARM] 3848/1: pxafb: Add option of fixing video modes and spitz QVGA mode support
  [ARM] 3880/1: remove the last trace of iop31x support
  [ARM] 3879/1: ep93xx: instantiate platform devices for ep93xx ethernet
  [ARM] 3809/3: get rid of 4 megabyte kernel image size limit
  [ARM] Fix XIP_KERNEL build error in arch/arm/mm/mmu.c
  [ARM] 3874/1: Remove leftover usage of asm/timeofday.h
2006-10-03 09:14:00 -07:00
Russell King
6ae5a6ef03 [ARM] Fix XIP_KERNEL build error in arch/arm/mm/mmu.c
XIP kernels need to know the start/end of text, but we were
missing the declaration of _etext in mmu.c.  Add it.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-30 10:50:05 +01:00
Sukadev Bhattiprolu
f400e198b2 [PATCH] pidspace: is_init()
This is an updated version of Eric Biederman's is_init() patch.
(http://lkml.org/lkml/2006/2/6/280).  It applies cleanly to 2.6.18-rc3 and
replaces a few more instances of ->pid == 1 with is_init().

Further, is_init() checks pid and thus removes dependency on Eric's other
patches for now.

Eric's original description:

	There are a lot of places in the kernel where we test for init
	because we give it special properties.  Most  significantly init
	must not die.  This results in code all over the kernel test
	->pid == 1.

	Introduce is_init to capture this case.

	With multiple pid spaces for all of the cases affected we are
	looking for only the first process on the system, not some other
	process that has pid == 1.

Signed-off-by: Eric W. Biederman <ebiederm@xmission.com>
Signed-off-by: Sukadev Bhattiprolu <sukadev@us.ibm.com>
Cc: Dave Hansen <haveblue@us.ibm.com>
Cc: Serge Hallyn <serue@us.ibm.com>
Cc: Cedric Le Goater <clg@fr.ibm.com>
Cc: <lxc-devel@lists.sourceforge.net>
Acked-by: Paul Mackerras <paulus@samba.org>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-09-29 09:18:12 -07:00
Jason Baron
df67b3daea [PATCH] make PROT_WRITE imply PROT_READ
Make PROT_WRITE imply PROT_READ for a number of architectures which don't
support write only in hardware.

While looking at this, I noticed that some architectures which do not
support write only mappings already take the exact same approach.  For
example, in arch/alpha/mm/fault.c:

"
        if (cause < 0) {
                if (!(vma->vm_flags & VM_EXEC))
                        goto bad_area;
        } else if (!cause) {
                /* Allow reads even for write-only mappings */
                if (!(vma->vm_flags & (VM_READ | VM_WRITE)))
                        goto bad_area;
        } else {
                if (!(vma->vm_flags & VM_WRITE))
                        goto bad_area;
        }
"

Thus, this patch brings other architectures which do not support write only
mappings in-line and consistent with the rest.  I've verified the patch on
ia64, x86_64 and x86.

Additional discussion:

Several architectures, including x86, can not support write-only mappings.
The pte for x86 reserves a single bit for protection and its two states are
read only or read/write.  Thus, write only is not supported in h/w.

Currently, if i 'mmap' a page write-only, the first read attempt on that page
creates a page fault and will SEGV.  That check is enforced in
arch/blah/mm/fault.c.  However, if i first write that page it will fault in
and the pte will be set to read/write.  Thus, any subsequent reads to the page
will succeed.  It is this inconsistency in behavior that this patch is
attempting to address.  Furthermore, if the page is swapped out, and then
brought back the first read will also cause a SEGV.  Thus, any arbitrary read
on a page can potentially result in a SEGV.

According to the SuSv3 spec, "if the application requests only PROT_WRITE, the
implementation may also allow read access." Also as mentioned, some
archtectures, such as alpha, shown above already take the approach that i am
suggesting.

The counter-argument to this raised by Arjan, is that the kernel is enforcing
the write only mapping the best it can given the h/w limitations.  This is
true, however Alan Cox, and myself would argue that the inconsitency in
behavior, that is applications can sometimes work/sometimes fails is highly
undesireable.  If you read through the thread, i think people, came to an
agreement on the last patch i posted, as nobody has objected to it...

Signed-off-by: Jason Baron <jbaron@redhat.com>
Cc: Russell King <rmk@arm.linux.org.uk>
Cc: "Luck, Tony" <tony.luck@intel.com>
Cc: Hugh Dickins <hugh@veritas.com>
Cc: Roman Zippel <zippel@linux-m68k.org>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Acked-by: Andi Kleen <ak@muc.de>
Acked-by: Alan Cox <alan@lxorguk.ukuu.org.uk>
Cc: Arjan van de Ven <arjan@linux.intel.com>
Acked-by: Paul Mundt <lethal@linux-sh.org>
Cc: Kazumoto Kojima <kkojima@rr.iij4u.or.jp>
Cc: Ian Molton <spyro@f2s.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-09-29 09:18:05 -07:00
Linus Torvalds
ebdea46fec Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (130 commits)
  [ARM] 3856/1: Add clocksource for Intel IXP4xx platforms
  [ARM] 3855/1: Add generic time support
  [ARM] 3873/1: S3C24XX: Add irq_chip names
  [ARM] 3872/1: S3C24XX: Apply consistant tabbing to irq_chips
  [ARM] 3871/1: S3C24XX: Fix ordering of EINT4..23
  [ARM] nommu: confirms the CR_V bit in nommu mode
  [ARM] nommu: abort handler fixup for !CPU_CP15_MMU cores.
  [ARM] 3870/1: AT91: Start removing static memory mappings
  [ARM] 3869/1: AT91: NAND support for DK and KB9202 boards
  [ARM] 3868/1: AT91 hardware header update
  [ARM] 3867/1: AT91 GPIO update
  [ARM] 3866/1: AT91 clock update
  [ARM] 3865/1: AT91RM9200 header updates
  [ARM] 3862/2: S3C2410 - add basic power management support for AML M5900 series
  [ARM] kthread: switch arch/arm/kernel/apm.c
  [ARM] Off-by-one in arch/arm/common/icst*
  [ARM] 3864/1: Refactore sharpsl_pm
  [ARM] 3863/1: Add Locomo SPI Device
  [ARM] 3847/2:  Convert LOMOMO to use struct device for GPIOs
  [ARM] Use CPU_CACHE_* where possible in asm/cacheflush.h
  ...
2006-09-28 14:40:39 -07:00
Hyok S. Choi
6afd6fae1d [ARM] nommu: confirms the CR_V bit in nommu mode
In nommu mode, the exception vector location depends on the platforms.
Some of the implementations may have some special exception control
forwarding method in their ROM/flash and for some of them has its own
re-mapping mechanism by the h/w.

This patch introduces a special configuration CONFIG_CPU_HIGH_VECTOR which
turns on the CR_V bit in nommu mode. The CR_V bit is turned off by default.
This feature depends on CP15 and does not supported by ARM740.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-28 20:17:30 +01:00
Hyok S. Choi
0f45d7f36b [ARM] nommu: abort handler fixup for !CPU_CP15_MMU cores.
There is no FSR/FAR register on no-CP15 or MPU cores. This patch adds a
dummy abort handler which returns zero for the base restored Data Abort
model !CPU_CP15_MMU cores. The abort-lv4t.S is still used with the fix-up
for the base updated Data Abort model cores.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-28 20:15:46 +01:00
Russell King
6b237a355a [ARM] Make !MMU CPUs depend on !MMU
Don't offer non-MMU based CPUs for selection when CONFIG_MMU is
set.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 17:44:39 +01:00
Hyok S. Choi
f37f46eb1c [ARM] nommu: add ARM946E-S core support
This patch adds ARM946E-S core support which has typically 8KB I&D cache.
It has a MPU and supports ARMv5TE instruction set.

Because the ARM946E-S core can be synthesizable with various cache size,
CONFIG_CPU_DCACHE_SIZE is defined for vendor specific configurations.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 17:39:19 +01:00
Hyok S. Choi
d60674eb5d [ARM] nommu: add ARM940T core support
This patch adds ARM940T core support which has 4KB D-cache, 4KB I-cache
and a MPU.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 17:39:18 +01:00
Hyok S. Choi
43f5f0146e [ARM] nommu: add ARM9TDMI core support
This patch adds ARM9TDMI core support which has no cache and no CP15
register(no memory control unit).

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 17:39:17 +01:00
Hyok S. Choi
b731c3118d [ARM] nommu: add ARM740T core support
This patch adds ARM740T core support which has a MPU and 4KB or 8KB cache.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 17:39:17 +01:00
Hyok S. Choi
07e0da78ab [ARM] nommu: add ARM7TDMI core support
This patch adds ARM7TDMI core support which has no cache and no CP15
register(no memory control unit).

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 17:39:17 +01:00
Hyok S. Choi
f12d0d7c77 [ARM] nommu: manage the CP15 things
All the current CP15 access codes in ARM arch can be categorized and
conditioned by the defines as follows:

     Related operation	Safe condition
  a. any CP15 access	!CPU_CP15
  b. alignment trap	CPU_CP15_MMU
  c. D-cache(C-bit)	CPU_CP15
  d. I-cache		CPU_CP15 && !( CPU_ARM610 || CPU_ARM710 ||
				CPU_ARM720 || CPU_ARM740 ||
				CPU_XSCALE || CPU_XSC3 )
  e. alternate vector	CPU_CP15 && !CPU_ARM740
  f. TTB		CPU_CP15_MMU
  g. Domain		CPU_CP15_MMU
  h. FSR/FAR		CPU_CP15_MMU

For example, alternate vector is supported if and only if
"CPU_CP15 && !CPU_ARM740" is satisfied.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 17:34:30 +01:00
Hyok S. Choi
fefdaa06cc [ARM] nommu: defines CPU_CP15, CPU_CP15_MMU and CPU_CP15_MPU
By merging of uClinux/ARM, we need to treat various CPU cores which have
MMU, MPU or even none for memory management. The memory management
coprocessors are controlled by CP15 register set and the ARM core family
can be categorized by 5 groups by the register ;
  G-a. CP15 is MMU : 610, 710, 720, 920, 922, 925, 926, 1020, 1020e, 1022,
		v6 and the derivations sa1100, sa110, xscale, xsc3.
  G-b. CP15 is MPU : 740, 940, 946, 996, 1156.
  G-c. CP15 is MPU or MMU : 1026 (selectable by schematic design)
  G-d. CP15 is exist, but nothing for memory managemnt : 966, 968.
  G-e. no-CP15 : 7tdmi, 9tdmi, 9e, 9ej

This patch defines CPU_CP15, CPU_CP15_MMU and CPU_CP15_MPU. Thus the
family can be defined as :
  - CPU_CP15 only : G-d
  - CPU_CP15_MMU(implies CPU_CP15) : G-a, G-c(selectable)
  - CPU_CP15_MPU(implies CPU_CP15) : G-b, G-c(selectable)
  - !CPU_CP15 : G-e

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 17:28:47 +01:00
Russell King
e5beac371a [ARM] do_bad_area() always takes current and current->active_mm
Since do_bad_area() always takes the currently active task and
(supposed to) take the currently active MM, there's no point passing
them to this function.  Instead, obtain references to them inside
do_bad_area().

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 16:13:48 +01:00
Russell King
80878d6c4a [ARM] Add setup_mm_for_reboot() for nommu
Add an empty setup_mm_for_reboot() function for nommu machines.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 15:43:47 +01:00
Russell King
0c668984dd [ARM] Rename mm-armv.c to pgd.c
mm-armv.c now only contains the pgd allocation/freeing code, so
rename it to have a more sensible filename.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 15:40:28 +01:00
Russell King
ae8f154129 [ARM] Move rest of MMU setup code from mm-armv.c to mmu.c
If we're going to have mmu.c for code which is specific to the MMU
machines, we might as well move the other MMU initialisation
specific code from mm-armv.c into this new file.  This also allows
us to make some functions static.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 15:38:34 +01:00
Russell King
d111e8f964 [ARM] Split ARM MM initialisation for !mmu
Move the MMU specific code from init.c into mmu.c, and add nommu
fixups to nommu.c

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 15:27:33 +01:00
Russell King
456335e207 [ARM] Separate page table manipulation code from bootmem initialisation
nommu does not require the page table manipulation code in the
bootmem initialisation paths.  Move this into separate inline
functions.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 10:10:58 +01:00
George G. Davis
4052ebb7a2 [ARM] 3859/1: Fix devicemaps_init() XIP_KERNEL odd 1MiB XIP_PHYS_ADDR translation error
The ARM XIP_KERNEL map created in devicemaps_init() is wrong.
The map.pfn is rounded down to an even 1MiB section boundary
which results in va/pa translations errors when XIP_PHYS_ADDR
starts on an odd 1MiB boundary and this causes the kernel to
hang.  This patch fixes ARM XIP_KERNEL translation errors for
the odd 1MiB XIP_PHYS_ADDR boundary case.

Signed-off-by: George G. Davis <gdavis@mvista.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-27 09:35:05 +01:00
Dave McCracken
46a82b2d55 [PATCH] Standardize pxx_page macros
One of the changes necessary for shared page tables is to standardize the
pxx_page macros.  pte_page and pmd_page have always returned the struct
page associated with their entry, while pte_page_kernel and pmd_page_kernel
have returned the kernel virtual address.  pud_page and pgd_page, on the
other hand, return the kernel virtual address.

Shared page tables needs pud_page and pgd_page to return the actual page
structures.  There are very few actual users of these functions, so it is
simple to standardize their usage.

Since this is basic cleanup, I am submitting these changes as a standalone
patch.  Per Hugh Dickins' comments about it, I am also changing the
pxx_page_kernel macros to pxx_page_vaddr to clarify their meaning.

Signed-off-by: Dave McCracken <dmccr@us.ibm.com>
Cc: Hugh Dickins <hugh@veritas.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-09-26 08:48:51 -07:00
George G. Davis
a71ebdfa52 [ARM] 3853/1: Fix flush_ptrace_access() thinko for nonaliasing VIPT cache case
Fix thinko in the flush_ptrace_access() "if (expr)" for the ARM
VIPT non-aliasing cache case.  We only need to flush cache when
VM_EXEC is set in vma->vm_flags but "if (expr) always evaluates
to true on UP systems for the ARM VIPT non-aliasing cache case.

Signed-off-by: George G. Davis <gdavis@mvista.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-25 10:34:04 +01:00
Lennert Buytenhek
3f7e5815f4 [ARM] 3817/1: iop3xx: split the iop3xx mach into iop32x and iop33x
Split the iop3xx mach type into iop32x and iop33x -- split the config
symbols, and move the code in the mach-iop3xx directory to the mach-iop32x
and mach-iop33x directories.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-25 10:25:36 +01:00
Lennert Buytenhek
197c9444d6 [ARM] 3814/1: move 80200 dma_inv_range() erratum check out of line
On stepping A0/A1 of the 80200, invalidating D-cache by line doesn't
clear the dirty bits, which means that if we invalidate a dirty line,
the dirty data can still be written back to memory later on.

To work around this, dma_inv_range() on these two processors is
implemented as dma_flush_range() (i.e. do a clean D-cache line before
doing the invalidate D-cache line.)  For this, we currently have a
processor ID check in xscale_dma_inv_range(), but a better solution
is to add a separate cache_fns and proc_info for A0/A1 80200.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-25 10:25:27 +01:00
Lennert Buytenhek
51635ad282 [ARM] 3813/1: prevent >= 4G /dev/mem mmap()
Prevent userland from mapping in physical address regions >= 4G by
checking for that in valid_mmap_phys_addr_range().

Unfortunately, we cannot override valid_mmap_phys_addr_range() without
also overriding valid_phys_addr_range(), so copy drivers/char/mem.c's
version of valid_phys_addr_range() over to arch/arm/mm/mmap.c as well.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-25 10:25:26 +01:00
Russell King
d84b47115a [ARM] Move mmu.c out of the way
Rename mmu.c to context.c - it's the ARMv6 ASID context handling
code rather than generic "mmu" handling code.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-20 14:58:35 +01:00
Russell King
1b2e2b73b4 [ARM] Cleanup arch/arm/mm a little
Move top_pmd into arch/arm/mm/mm.h - nothing outside arch/arm/mm
references it.

Move the repeated definition of TOP_PTE into mm/mm.h, as well as
a few function prototypes.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-20 14:58:35 +01:00
Dan Williams
36694a4c22 [ARM] 3780/1: Fix iop321 cpuid
Patch from Dan Williams

commit a6a38a6622 changed the iop321 id to a value that does not work with all platforms.  Change the mask to permit bit 11.  Tested on an iq80321 600Mhz CRB.

Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-14 17:45:16 +01:00
Catalin Marinas
f854d37ab6 [ARM] 3773/1: Add the HWCAP_VFP bit for the ARM926 CPUs
Patch from Catalin Marinas

The ARM926EJ-S CPU has the VFP coprocessor and therefore it should be shown
in the /proc/cpuinfo if CONFIG_VFP is enabled.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-06 19:03:28 +01:00
George G. Davis
a188ad2bc7 [ARM] 3762/1: Fix ptrace cache coherency bug for ARM1136 VIPT nonaliasing Harvard caches
Patch from George G. Davis

Resolve ARM1136 VIPT non-aliasing cache coherency issues observed when
using ptrace to set breakpoints and cleanup copy_{to,from}_user_page()
while we're here as requested by Russell King because "it's also far
too heavy on non-v6 CPUs".

NOTES:

1. Only access_process_vm() calls copy_{to,from}_user_page().
2. access_process_vm() calls get_user_pages() to pin down the "page".
3. get_user_pages() calls flush_dcache_page(page) which ensures cache
   coherency between kernel and userspace mappings of "page".  However
   flush_dcache_page(page) may not invalidate I-Cache over this range
   for all cases, specifically, I-Cache is not invalidated for the VIPT
   non-aliasing case.  So memory is consistent between kernel and user
   space mappings of "page" but I-Cache may still be hot over this
   range.  IOW, we don't have to worry about flush_cache_page() before
   memcpy().
4. Now, for the copy_to_user_page() case, after memcpy(), we must flush
   the caches so memory is consistent with kernel cache entries and
   invalidate the I-Cache if this mm region is executable.  We don't
   need to do anything after memcpy() for the copy_from_user_page()
   case since kernel cache entries will be invalidated via the same
   process above if we access "page" again.  The flush_ptrace_access()
   function (borrowed from SPARC64 implementation) is added to handle
   cache flushing after memcpy() for the copy_to_user_page() case.

Signed-off-by: George G. Davis <gdavis@mvista.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-09-02 18:43:20 +01:00
Lennert Buytenhek
260e98edc8 [ARM] 3761/1: fix armv4t breakage after adding thumb interworking to userspace helpers
Patch from Lennert Buytenhek

On armv4t systems, we have always compiled the kernel with -march=armv4
instead of -march=armv4t, which means that any use of bx will bomb out.

Commit ba9b5d7637 introduced the use of
bx in the kernel, which means we need to compile with -march=armv4t on
armv4t systems now.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-08-28 12:51:20 +01:00
Catalin Marinas
ceaccbd2a6 [ARM] 3734/1: Fix the unused variable warning in __iounmap()
Patch from Catalin Marinas

This patch adds #ifdef around some variables in the arch/arm/mm/ioremap.c
file.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-07-29 08:29:30 +01:00
George G. Davis
7b1df1985c [ARM] 3737/1: Export ARM copy/clear_user_page symbols
Patch from George G. Davis

As reported by various folks on the ARM Linux kernel mailing list,
the video-buf.ko driver has undefined references on all ARM machines
which use it as observed during `make modules`:

Warning: "v4wb_clear_user_page" [drivers/media/video/video-buf.ko] undefined!

Similar warnings exist for all ARM machines which use this driver.
So this change adds the missing EXPORT_SYMBOLs to allow using this
driver as a module.

Signed-off-by: George G. Davis <gdavis@mvista.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-07-29 08:29:27 +01:00
Lennert Buytenhek
a6a38a6622 [ARM] 3736/1: xscale: don't mis-report 80219 as an iop32x
Patch from Lennert Buytenhek

The IOP 80219 xscale CPU is a stripped down version of the IOP32x.
But the fact that the 80219 and IOP32x are very similar doesn't mean
that they need to share a cpu table entry.  It's also somewhat confusing
for the end user to see the 80219 reported as an IOP32x, so this patch
splits the IOP32x cpu table entry to make a separate entry for the
80219.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-07-29 08:29:26 +01:00
Russell King
67f3a58856 [ARM] Fix warning in consistent.c
No need for 'cr' to be a local variable, which is unused in the
SMP case, and only used once in the UP case.  Just call get_cr()
directly.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-07-03 13:30:52 +01:00
Russell King
906243d07b [ARM] Fix bad asm instruction in proc-arm925.S
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-07-03 12:44:30 +01:00
Russell King
00eb0f6b65 [ARM] More missing proc-macros.S includes
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-07-03 12:36:07 +01:00
Lennert Buytenhek
7cddc39702 [ARM] 3708/2: fix SMP build after section ioremap changes
Patch from Lennert Buytenhek

Commit ff0daca525 broke the SMP build,
this patch fixes it up again.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-07-03 12:26:02 +01:00
Thomas Gleixner
bb8d5a55a5 [PATCH] ARM: Fixup missing includes in arch/arm/mm/proc-<cputype>.S
For several proc-<cputype>.S files the include of proc-macros.S is
missing. Make it compile and work again.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-07-02 17:29:22 -07:00
Linus Torvalds
a8c4c20dfa Merge branch 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm
* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (44 commits)
  [ARM] 3541/2: workaround for PXA27x erratum E7
  [ARM] nommu: provide a way for correct control register value selection
  [ARM] 3705/1: add supersection support to ioremap()
  [ARM] 3707/1: iwmmxt: use the generic thread notifier infrastructure
  [ARM] 3706/2: ep93xx: add cirrus logic edb9315a support
  [ARM] 3704/1: format IOP Kconfig with tabs, create more consistency
  [ARM] 3703/1: Add help description for ARCH_EP80219
  [ARM] 3678/1: MMC: Make OMAP MMC work
  [ARM] 3677/1: OMAP: Update H2 defconfig
  [ARM] 3676/1: ARM: OMAP: Fix dmtimers and timer32k to compile on OMAP1
  [ARM] Add section support to ioremap
  [ARM] Fix sa11x0 SDRAM selection
  [ARM] Set bit 4 on section mappings correctly depending on CPU
  [ARM] 3666/1: TRIZEPS4 [1/5] core
  ARM: OMAP: Multiplexing for 24xx GPMC wait pin monitoring
  ARM: OMAP: Fix SRAM to use MT_MEMORY instead of MT_DEVICE
  ARM: OMAP: Update dmtimers
  ARM: OMAP: Make clock variables static
  ARM: OMAP: Fix GPMC compilation when DEBUG is defined
  ARM: OMAP: Mux updates for external DMA and GPIO
  ...
2006-07-02 15:04:12 -07:00
Nicolas Pitre
2dc7667b9d [ARM] 3541/2: workaround for PXA27x erratum E7
Patch from Nicolas Pitre

According to the Intel PXA27x Processor Family Specification
Update document (doc.nr. 280071-009) erratum E7, some care must be taken
to locate the disabling and re-enabling of the MMU to the beginning of a
cache line to avoid problems in some circumstances.

Credits to Simon Vogl <simon.vogl@researchstudios.at> for bringing this
up.

Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-07-01 21:29:32 +01:00
Russell King
3f8efdbe73 Merge nommu branch 2006-07-01 20:43:57 +01:00
Lennert Buytenhek
a069c896d0 [ARM] 3705/1: add supersection support to ioremap()
Patch from Lennert Buytenhek

Analogous to the previous patch that allows ioremap() to use section
mappings, this patch allows ioremap() to use supersection mappings.
Original patch by Deepak Saxena.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-07-01 19:58:20 +01:00
Linus Torvalds
22a3e233ca Merge git://git.kernel.org/pub/scm/linux/kernel/git/bunk/trivial
* git://git.kernel.org/pub/scm/linux/kernel/git/bunk/trivial:
  Remove obsolete #include <linux/config.h>
  remove obsolete swsusp_encrypt
  arch/arm26/Kconfig typos
  Documentation/IPMI typos
  Kconfig: Typos in net/sched/Kconfig
  v9fs: do not include linux/version.h
  Documentation/DocBook/mtdnand.tmpl: typo fixes
  typo fixes: specfic -> specific
  typo fixes in Documentation/networking/pktgen.txt
  typo fixes: occuring -> occurring
  typo fixes: infomation -> information
  typo fixes: disadvantadge -> disadvantage
  typo fixes: aquire -> acquire
  typo fixes: mecanism -> mechanism
  typo fixes: bandwith -> bandwidth
  fix a typo in the RTC_CLASS help text
  smb is no longer maintained

Manually merged trivial conflict in arch/um/kernel/vmlinux.lds.S
2006-06-30 15:39:30 -07:00
Christoph Lameter
df849a1529 [PATCH] zoned vm counters: conversion of nr_pagetables to per zone counter
Conversion of nr_page_table_pages to a per zone counter

[akpm@osdl.org: bugfix]
Signed-off-by: Christoph Lameter <clameter@sgi.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-06-30 11:25:35 -07:00
Jörn Engel
6ab3d5624e Remove obsolete #include <linux/config.h>
Signed-off-by: Jörn Engel <joern@wohnheim.fh-wedel.de>
Signed-off-by: Adrian Bunk <bunk@stusta.de>
2006-06-30 19:25:36 +02:00
Russell King
ff0daca525 [ARM] Add section support to ioremap
Allow section mappings to be setup using ioremap() and torn down
with iounmap().  This requires additional support in the MM
context switch to ensure that mappings are properly synchronised
when mapped in.

Based an original implementation by Deepak Saxena, reworked and
ARMv6 support added by rmk.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-29 22:14:30 +01:00
Russell King
8799ee9f49 [ARM] Set bit 4 on section mappings correctly depending on CPU
On some CPUs, bit 4 of section mappings means "update the
cache when written to".  On others, this bit is required to
be one, and others it's required to be zero.  Finally, on
ARMv6 and above, setting it turns on "no execute" and prevents
speculative prefetches.

With all these combinations, no one value fits all CPUs, so we
have to pick a value depending on the CPU type, and the area
we're mapping.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-29 18:24:21 +01:00
Andrew Victor
8fc5ffa063 [ARM] 3675/2: Preparing for AT91SAM926 support
Patch from Andrew Victor

This prepares the way for adding support for the new Atmel AT91SAM926x
processors.

Major changes:
- Rename time.c to at91rm9200_time.c
- Rename common.c to at91rm9200.c
- Introduce ARCH_AT91, of which ARCH_AT91RM9200, ARCH_AT91SAM9260 and
ARCH_AT91SAM9261 are dependent.

Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-29 16:06:33 +01:00
Russell King
22b1908610 [ARM] nommu: provide a way for correct control register value selection
Most MMU-based CPUs have a restriction on the setting of the data cache
enable and mmu enable bits in the control register, whereby if the data
cache is enabled, the MMU must also be enabled.  Enabling the data
cache without the MMU is an invalid combination.

However, there are CPUs where the data cache can be enabled without the
MMU.

In order to allow these CPUs to take advantage of that, provide a
method whereby each proc-*.S file defines the control regsiter value
for use with nommu (with the MMU disabled.)  Later on, when we add
support for enabling the MMU on these devices, we can adjust the
"crval" macro to also enable the data cache for nommu.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-29 15:09:57 +01:00
Russell King
264edb35ce [ARM] Remove yucky ifdefs to print "id(wb)BRR" suffix on CPU name
The "id(wb)BRR" suffix reports which CPU debugging options were (or
were not) selected at kernel build time.  Rather than have every
proc-*.S file implement this, report the control register value,
from which this information can be deduced.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-29 15:03:09 +01:00
Hyok S. Choi
d090dddaba [ARM] nommu: Initial uCLinux support for MMU-based CPUs
In noMMU mode, various of functions which are defined in mm/proc-*.S
is not valid or needed to be avoided. i.g. switch_mm is not needed,
just returns and this makes the I & D caches are valid which shows
great improvement of performance including task switching and IPC.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-28 17:59:56 +01:00
Hyok S. Choi
3e36122595 [ARM] nommu: export flush_dcache_page()
This is a trivial patch to export flush_dcache_page in mm/nommu.c.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-28 17:59:53 +01:00
Russell King
092c1952e1 [ARM] nommu: remove fault-armv, mmap and mm-armv files from nommu build
Remove fault-armv.o, mmap.o and mm-armv.o from uclinux builds - these
are concerned with MMU-ful operations, and as such are redundant for
uclinux.

Since this also removes iotable_init() and iotable_init() is used
extensively in the platform support files, just make it a no-op.

Based upon a couple of patches by Hyok.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-28 17:59:52 +01:00
Russell King
888e7bf166 [ARM] Remove TABLE_SIZE, and several unused function prototypes
TABLE_SIZE is never used in arch/arm/mm/init.c.  create_memmap_holes(),
memtable_init, and setup_io_desc() no longer exist in the kernel.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-28 17:59:51 +01:00
Russell King
e6b1b38c52 [ARM] nommu: Provide a simple flush_dcache_page implementation
nommu doesn't require a complex flush_dcache_page implementation
like the MMU-ful CPUs do, so provide a simplified version in nommu.c
and omit flush.c from the build as appropriate.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-28 17:59:50 +01:00
Russell King
5924486dc0 [ARM] nommu: add stubs for ioremap and friends
nommu doesn't have any form of remapping support, so ioremap, etc
become stubs which just return the casted address, doing nothing
else.

Move ioport_map(), ioport_unmap(), pci_iomap(), pci_iounmap()
into a separate file which is always built.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-28 17:59:48 +01:00
Hyok S. Choi
f9c21a6ee7 [ARM] nommu: avoid selecting TLB and CPU specific copy code
Since uclinux doesn't make use of the TLB, including the TLB
maintainence and CPU-optimised copypage functions does not
make sense.  Remove them.

(This is part of one of Hyok's patches.)

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-28 17:59:47 +01:00
Russell King
60b6cf6851 [ARM] nommu: we need the TLS register emulation for nommu mode
Since there can be no fixed location for the TLS value with nommu
systems, we must provide TLS register emulation in order to support
TLS binaries on CPUs without the thread register.

Part of a patch from Hyok S. Choi, and cleaned up by rmk.

Signed-off-by: Hyok S. Choi <hyok.choi@samsung.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-28 17:59:43 +01:00
Russell King
800d8b5c4b [ARM] Remove partial non-v6 binutils compatibility
proc-v6 contains some compatibility to be able to use the V6
"cps" instruction.  However, the kernel makes use of this
instruction elsewhere extensively, so there's no point keeping
this compatibility anymore.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-25 11:31:22 +01:00
Russell King
1b93a71755 [ARM] Remove LOADREGS macro
As for RETINSTR, LOADREGS is a left-over from the 26-bit days.
Remove it.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-25 11:23:45 +01:00
Ben Dooks
3434d9d9fc [ARM] 3636/1: S3C2412: Add selection of CPU_ARM926
Patch from Ben Dooks

Select CONFIG_CPU_ARM926 when CONFIG_CPU_S3C2412 is
selected.

Signed-off-by: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-24 21:21:28 +01:00
Sascha Hauer
bb6d8c8828 [ARM] 3567/2: arm: base support for Hilscher netX
Patch from Sascha Hauer

This patch adds the base support for Hilscher's netX network
processors.

Signed-off-by: Robert Schwebel <r.schwebel@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-19 15:27:53 +01:00
Vitaly Wool
78818e477b [ARM] 3466/1: [2/3] Support for Philips PNX4008 platform: chip support
Patch from Vitaly Wool

This patch adds basic chip support for PNX4008 ARM platform.
It's basically the same as the previous one, but with the rmk's
comments taken into account.

Signed-off-by: Vitaly Wool <vwool@ru.mvista.com>
Signed-off-by: Dmitry Pervushin <dpervushin@gmail.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-06-18 16:16:55 +01:00
Deepak Saxena
5cedae9ca7 [PATCH] ARM: Fix XScale PMD setting
The ARM Architecture Reference Manual lists bit 4 of the PMD as "implementation
defined" and it must be set to zero on Intel XScale CPUs or the cache does
not behave properly. Found by Mike Rapoport while debugging a flash issue
on the PXA255:

	http://marc.10east.com/?l=linux-arm-kernel&m=114845287600782&w=1

Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-05-31 16:27:44 -07:00
Deepak Saxena
e6ed89ac9f [PATCH] ARM: explicitly disable BTB on ixp2350
We don't enable the BTB on the ixp2350 as that can cause weird
crashes (erratum #42.)  However, some bootloaders enable the BTB,
which means that we have to disable the BTB explicitly.

Found thanks to Tom Rini.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-05-30 20:33:20 -07:00
Catalin Marinas
478922c2b3 [ARM] 3526/1: ioremap should use vunmap instead of vfree on ARM
Patch from Catalin Marinas

This patch modifies the __ioremap_pfn and __iounmap functions in
arch/arm/mm/ioremap.c to use vunmap instead of vfree.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-05-16 11:39:31 +01:00
Russell King
95f3df6bcb [ARM] Fix SA110/SA1100 cache flushing
We had two implementations for flushing the cache, which meant StrongARM
caches weren't being correctly flushed.  Fix this by always using the
v4wb_flush_kern_cache_all method, rather than duplicating it.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-04-07 13:23:57 +01:00
Russell King
74d02fb954 [ARM] Move FLUSH_BASE macros to asm/arch/memory.h
FLUSH_BASE must be visible to arch/arm/mm/init.c in order for the
memory region to be setup.  Move these definitions from
asm-arm/arch-*/hardware.h into asm-arm/arch-*/memory.h where mm
stuff can see them.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-04-07 13:22:21 +01:00
Lennert Buytenhek
23759dc643 [ARM] 3439/2: xsc3: add I/O coherency support
Patch from Lennert Buytenhek

This patch adds support for the I/O coherent cache available on the
xsc3.  The approach is to provide a simple API to determine whether the
chipset supports coherency by calling arch_is_coherent() and then
setting the appropriate system memory PTE and PMD bits.  In addition,
we call this API on dma_alloc_coherent() and dma_map_single() calls.
A generic version exists that will compile out all the coherency-related
code that is not needed on the majority of ARM systems.

Note that we do not check for coherency in the dma_alloc_writecombine()
function as that still requires a special PTE setting.  We also don't
touch dma_mmap_coherent() as that is a special ARM-only API that is by
definition only used on non-coherent system.

Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-04-02 00:07:39 +01:00
Lennert Buytenhek
b48340aff0 [ARM] 3425/1: xsc3: need to include pgtable-hwdef.h
Patch from Lennert Buytenhek

Adapt xsc3 to the changes in 74945c8616
(xsc3 was written before but merged after the latter went in.)

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-30 10:24:07 +01:00
Lennert Buytenhek
23bdf86aa0 [ARM] 3377/2: add support for intel xsc3 core
Patch from Lennert Buytenhek

This patch adds support for the new XScale v3 core.  This is an
ARMv5 ISA core with the following additions:

- L2 cache
- I/O coherency support (on select chipsets)
- Low-Locality Reference cache attributes (replaces mini-cache)
- Supersections (v6 compatible)
- 36-bit addressing (v6 compatible)
- Single instruction cache line clean/invalidate
- LRU cache replacement (vs round-robin)

I attempted to merge the XSC3 support into proc-xscale.S, but XSC3
cores have separate errata and have to handle things like L2, so it
is simpler to keep it separate.

L2 cache support is currently a build option because the L2 enable
bit must be set before we enable the MMU and there is no easy way to
capture command line parameters at this point.

There are still optimizations that can be done such as using LLR for
copypage (in theory using the exisiting mini-cache code) but those
can be addressed down the road.

Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-28 21:00:40 +01:00
Russell King
3747b36eea [ARM] proc-v6: mark page table walks outer-cacheable, shared. Enable NX.
Mark page table walks with outer-cacheable attribute, and enable no-execute
in page tables.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-27 16:59:07 +01:00
Russell King
0003cedfc5 Merge nommu tree
Fix merge conflict in arch/arm/mm/proc-xscale.S

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-25 22:08:55 +00:00
Linus Torvalds
591eb85ecd Merge master.kernel.org:/home/rmk/linux-2.6-arm
* master.kernel.org:/home/rmk/linux-2.6-arm: (45 commits)
  [ARM] 3389/1: typo and grammar fix
  [ARM] 3386/1: AT91RM9200 Clock update
  [ARM] 3384/1: AT91RM9200: Timer
  [ARM] 3382/1: ixp2000: unify defconfigs
  [ARM] 3381/1: ixp2000: fix slowport write timing control register fields
  [ARM] 3380/1: ixp2000: simplify ixdp2x00_master_npu() check
  [ARM] 3379/1: ixp2000: use generic 8250 debug macros
  [ARM] 3378/1: ixp2000: fix gpio interrupt handling
  [ARM] Quieten spurious IRQ detection
  [ARM] Use kcalloc to allocate counter_config array rather than kmalloc
  [ARM] Oprofile: dynamically allocate counter_config
  [ARM] Oprofile: Convert semaphore to mutex
  [ARM] 3376/2: S3C2410 - update defconfig
  [ARM] 3375/1: S3C2440 - fix osiris machine build
  [ARM] 3374/1: ep93xx: gpio interrupt support
  [ARM] 3361/1: S3C24XX - add USB bus clock source
  [ARM] 3360/1: S3C2440 - add set rate methods and camera clock
  [ARM] 3359/1: S3C24XX - add support for clk_set_rate
  [ARM] Convert kmalloc+memset to kzalloc
  [ARM] 3373/1: move uengine loader to arch/arm/common
  ...
2006-03-22 17:32:09 -08:00
Nick Piggin
7835e98b2e [PATCH] remove set_page_count() outside mm/
set_page_count usage outside mm/ is limited to setting the refcount to 1.
Remove set_page_count from outside mm/, and replace those users with
init_page_count() and set_page_refcounted().

This allows more debug checking, and tighter control on how code is allowed
to play around with page->_count.

Signed-off-by: Nick Piggin <npiggin@suse.de>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-03-22 07:54:02 -08:00
Nick Piggin
8dfcc9ba27 [PATCH] mm: split highorder pages
Have an explicit mm call to split higher order pages into individual pages.
 Should help to avoid bugs and be more explicit about the code's intention.

Signed-off-by: Nick Piggin <npiggin@suse.de>
Cc: Russell King <rmk@arm.linux.org.uk>
Cc: David Howells <dhowells@redhat.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: "David S. Miller" <davem@davemloft.net>
Cc: Chris Zankel <chris@zankel.net>
Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2006-03-22 07:53:57 -08:00
Lennert Buytenhek
e7736d47a1 [ARM] 3369/1: ep93xx: add core cirrus ep93xx support
Patch from Lennert Buytenhek

This patch adds support for the Cirrus ep93xx series of CPUs.  The
ep93xx is an ARM920T based CPU with two VICs, PL010 based UARTs,
IrDA, MaverickCrunch floating point coprocessor, between 24 and 64
GPIOs, ethernet, OHCI USB and, depending on the model, pcmcia, raster
engine, graphics accelerator, IDE controller and a bunch of other
stuff.

This patch adds the core ep93xx support code, and support for the
Glomation GESBC-9312-sx and the Technologic Systems TS-72xx SBCs.

Signed-off-by: Lennert Buytenhek <buytenh@wantstofly.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-21 22:06:11 +00:00
Russell King
f78f104368 [ARM] Remove unnecessary asm/hardware.h includes
asm/hardware.h is not required for the majority of processor support
files, ioremap support, mm initialisation, acorn IO support, nor
the debug code (which picks up its machine specific includes via
debug-macros.S)

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-21 22:05:50 +00:00
Russell King
48fa14f761 [ARM] select TLS_REG_EMUL and NEEDS_SYSCALL_FOR_CMPXCHG
Rather than having a growing dependency line, use select to set
these configuration symbols.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-21 22:03:26 +00:00
Russell King
74945c8616 [ARM] nommu: Move hardware page table definitions to pgtable-hwdef.h
Move the hardware PMD and PTE page table definitions from pgtable.h
into pgtable-hwdef.h, and include pgtable-hwdef.h as necessary.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-21 22:03:25 +00:00
Catalin Marinas
141fa40cff [ARM] 3356/1: Workaround for the ARM1136 I-cache invalidation problem
Patch from Catalin Marinas

ARM1136 erratum 371025 (category 2) specifies that, under rare
conditions, an invalidate I-cache by MVA (line or range) operation can
fail to invalidate a cache line. The recommended workaround is to
either invalidate the entire I-cache or invalidate the range by
set/way rather than MVA.

Note that for a 16K cache size, invalidating a 4K page by set/way is
equivalent to invalidating the entire I-cache.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-10 22:26:47 +00:00
Catalin Marinas
6a0e243069 [ARM] 3352/1: DSB required for the completion of a TLB maintenance operation
Patch from Catalin Marinas

Chapter B2.7.3 in the latest ARM ARM (with v6 information) states that
the completion of a TLB maintenance operation is only guaranteed by
the execution of a DSB (Data Syncronization Barrier, formerly Data
Write Barrier or Drain Write Buffer).

Note that a DSB is only needed in the flush_tlb_kernel_* functions
since the completion is guaranteed by a mode change (i.e. switching
back to user mode) for the flush_tlb_user_* functions.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-03-07 14:42:27 +00:00
Russell King
43cc19816b [ARM] CONFIG_CPU_MPCORE -> CONFIG_CPU_32v6K
CONFIG_CPU_MPCORE has never been a configuration symbol - it should
be CONFIG_CPU_32v6K.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-02-22 21:13:28 +00:00
Nicolas Pitre
18afea04f1 [ARM] 3294/1: don't invalidate individual BTB entries on ARMv6
Patch from Nicolas Pitre

Doing so adds a much larger cost to the loop than the cost implied by
simply invalidating the whole BTB at once.

Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-02-01 19:26:01 +00:00
Nicolas Pitre
8a052e0bc2 [ARM] 3293/1: don't invalidate the whole I-cache with xscale_coherent_user_range
Patch from Nicolas Pitre

The mini I-cache issue is valid only for kernel space since debuggers
would not fly if they used user space addresses for their stubs.

Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-02-01 19:26:01 +00:00
George G. Davis
7efb83002b [ARM] 3269/1: Add ARMv6 MT_NONSHARED_DEVICE mem_types[] index
Patch from George G. Davis

This Freescale Semiconductor, Inc. contributed patch adds mem_types[]
support for ARMv6 non-shared device memory region attributes. This
implementation provides support for only first level section mapped
non-shared devices. Second level non-shared device mappings are not
yet supported.

Signed-off-by: George G. Davis <gdavis@mvista.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-01-26 15:21:28 +00:00
Russell King
20a2c88f50 [ARM] Fix ioremap.c vfree type warning
arch/arm/mm/ioremap.c:145: warning: passing argument 1 of 'vfree' makes pointer from integer without a cast

resulted from commit id 9d4ae7276a

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-01-20 20:52:50 +00:00
Kevin Hilman
37134cd55d [ARM] 3209/1: Configurable DMA-consistent memory region
Patch from Kevin Hilman

This patch increase available DMA-consistent memory allocated by dma_coherent_alloc(). The default remains at 2M (defined in asm/memory.h) and each platform has the ability to override in asm/arch-foo/memory.h.

Signed-off-by: Kevin Hilman <kevin@hilman.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-01-12 16:12:21 +00:00
Deepak Saxena
9d4ae7276a [ARM] 3070/2: Add __ioremap_pfn() API
Patch from Deepak Saxena

In working on adding 36-bit addressed supersection support to ioremap(),
I came to the conclusion that it would be far simpler to do so by just
splitting __ioremap() into a main external interface and adding an
__ioremap_pfn() function that takes a pfn + offset into the page that
__ioremap() can call. This way existing callers of __ioremap() won't have
to change their code and 36-bit systems will just call __ioremap_pfn()
and we will not have to deal with unsigned long long variables.

Note that __ioremap_pfn() should _NOT_ be called directly by drivers
but is reserved for use by arch_ioremap() implementations that map
32-bit resource regions into the real 36-bit address and then call
this new function.

Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-01-09 19:23:11 +00:00
SAN People
73a59c1c4a [ARM] 3240/2: AT91RM9200 support for 2.6 (Core)
Patch from SAN People

Following changes were made to clock.c:

1) Replaced <asm/hardware/clock.h> with <linux/clk.h>
2) Removed old unused clk_enable & clk_disable.
3) Replaced clk_use/clk_unuse with clk_enable/clk_disable.

Otherwise it's the same as the previous patch.

Signed-off-by: Andrew Victor <andrew@sanpeople.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-01-09 17:05:41 +00:00
Russell King
0fec53a24a [ARM] Remove EPXA10DB machine support
EPXA10DB seems to be uncared for:
- the "PLD" code has never been merged
- no one has reported that this platform has been broken since
  at least 2.6.10
- interest seems to have dried up around March 2003.

Therefore, remove EPXA10DB support.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-01-08 22:37:46 +00:00
Russell King
78ff18a412 [ARM] Cleanup ARM includes
arch/arm/kernel/entry-armv.S has contained a comment suggesting
that asm/hardware.h and asm/arch/irqs.h should be moved into the
asm/arch/entry-macro.S include.  So move the includes to these
two files as required.

Add missing includes (asm/hardware.h, asm/io.h) to asm/arch/system.h
includes which use those facilities, and remove asm/io.h from
kernel/process.c.

Remove other unnecessary includes from arch/arm/kernel, arch/arm/mm
and arch/arm/mach-footbridge.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2006-01-03 17:39:34 +00:00
Russell King
df2f5e721e [ARM SMP] Disable lazy flush_dcache_page for SMP
Lazy flush_dcache_page() causes userspace instability on SMP
platforms, so disable it for now.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-30 16:02:54 +00:00
Russell King
5edf71ae12 [ARM] Do not call flush_tlb_kernel_range() with IRQs disabled.
We must not call TLB maintainence operations with interrupts disabled,
otherwise we risk a lockup in the SMP IPI code.

This means that consistent_free() can not be called from a context with
IRQs disabled.  In addition, we must not hold the lock in consistent_free
when we call flush_tlb_kernel_range().  However, we must continue to
prevent consistent_alloc() from re-using the memory region until we've
finished tearing down the mapping and dealing with the TLB.

Therefore, leave the vm_region entry in the list, but mark it inactive
before dropping the lock and starting the tear-down process.  After the
mapping has been torn down, re-acquire the lock and remove the entry
from the list.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-25 15:52:51 +00:00
Daniel Jacobowitz
a6c61e9dfd [ARM] 3168/1: Update ARM signal delivery and masking
Patch from Daniel Jacobowitz

After delivering a signal (creating its stack frame) we must check for
additional pending unblocked signals before returning to userspace.
Otherwise signals may be delayed past the next syscall or reschedule.

Once that was fixed it became obvious that the ARM signal mask manipulation
was broken.  It was a little bit broken before the recent SA_NODEFER
changes, and then very broken after them.  We must block the requested
signals before starting the handler or the same signal can be delivered
again before the handler even gets a chance to run.

Signed-off-by: Daniel Jacobowitz <dan@codesourcery.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-19 10:01:07 +00:00
Russell King
02b3083922 [ARM] Fix some corner cases in new mm initialisation
Document that the VMALLOC_END address must be aligned to 2MB since
it must align with a PGD boundary.

Allocate the vectors page early so that the flush_cache_all() later
will cause any dirty cache lines in the direct mapping will be safely
written back.

Move the flush_cache_all() to the second local_flush_cache_tlb() and
remove the now redundant first local_flush_cache_tlb().

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-17 22:43:30 +00:00
Russell King
67a1901ff4 [ARM] __ioremap doesn't use 4th argument
The "align" argument in ARMs __ioremap is unused and provides a
misleading expectation that it might do something.  It doesn't.
Remove it.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-17 16:48:00 +00:00
Tony Lindgren
1dbae815a7 [ARM] 3145/1: OMAP 3a/5: Add support for omap24xx
Patch from Tony Lindgren

This patch adds support for omap24xx series of processors.
The files live in arch/arm/mach-omap2, and share common
files with omap15xx and omap16xx processors in
arch/arm/plat-omap.

Omap24xx support was originally added for 2.6.9 by TI.
This code was then improved and integrated to share common
code with omap15xx and omap16xx processors by various
omap developers, such as Paul Mundt, Juha Yrjola, Imre Deak,
Tony Lindgren, Richard Woodruff, Nishant Menon, Komal Shah
et al.

Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-10 14:26:51 +00:00
Tony Lindgren
3179a01939 [ARM] 3141/1: OMAP 1/5: Update omap1 specific files
Patch from Tony Lindgren

This patch syncs the mainline kernel with linux-omap tree.
The highlights of the patch are:

- Omap1 serial pport and framebuffer init updates by Imre Deak

- Add support for omap310 processor and Palm Tungsten E PDA
  by Laurent Gonzales, Romain Goyet, et al. Omap310 and
  omap1510 processors are now handled as omap15xx.

- Omap1 specific changes to shared omap clock framework
  by Tony Lindgren

- Omap1 specific changes to shared omap pin mux framework
  by Tony Lindgren

- Other misc fixes, such as update memory timings for smc91x,
  omap1 specific device initialization etc.

Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-10 14:26:48 +00:00
Russell King
862184fe01 [ARM SMP] Add Realview MPcore SMP support
Add SMP support for the MPcore tile fitted to the Realview ARM
platform.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-07 21:05:42 +00:00
Russell King
cd03adb081 [ARM SMP] Add support for shared memory attribute
We need to set the shared memory attribute in the page tables
on SMP systems to allow the cache coherency to operate.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-07 10:10:28 +00:00
Russell King
5f8b1178e2 [ARM] Merge SMP tree 2005-11-03 21:02:39 +00:00
Nicolas Pitre
24bcc2f46c [ARM] 3092/1: remove excessive print format padding
Patch from Nicolas Pitre

Using a llx format to print addresses that might possibly be (only) 36
bits wide make sense.  However making it a zero padded 16 char wide
field is a bit excessive and useless.

Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-03 20:40:50 +00:00
Russell King
4a5f79e7e6 [ARM SMP] Add configuration option for ARMv6K processors
The 'K' extension adds several new instructions to the ARMv6 ISA
which are primerily useful for SMP.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-03 15:48:21 +00:00
Russell King
6bf7bd6967 [ARM] Fix mm initialisation with write buffered write allocate caches
It seems that without the extra tlb flush, we may end up faulting
during the early kernel initialisation because the TLB can't see
the updated page tables.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-11-02 14:11:35 +00:00
Catalin Marinas
8ad68bbf7a [ARM] Add support for ARM RealView board
Support for RealView EB.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-31 14:25:02 +00:00
Russell King
b4c2803ca8 [ARM] Make v6 copypage function static and cleanup pgprots
We know what pgprot we're going to use, so don't #define it.  Also,
since we select the nonaliasing/aliasing copypage implementation at
run time, there's no point having it globally visible.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-30 19:03:21 +00:00
Hugh Dickins
4c21e2f244 [PATCH] mm: split page table lock
Christoph Lameter demonstrated very poor scalability on the SGI 512-way, with
a many-threaded application which concurrently initializes different parts of
a large anonymous area.

This patch corrects that, by using a separate spinlock per page table page, to
guard the page table entries in that page, instead of using the mm's single
page_table_lock.  (But even then, page_table_lock is still used to guard page
table allocation, and anon_vma allocation.)

In this implementation, the spinlock is tucked inside the struct page of the
page table page: with a BUILD_BUG_ON in case it overflows - which it would in
the case of 32-bit PA-RISC with spinlock debugging enabled.

Splitting the lock is not quite for free: another cacheline access.  Ideally,
I suppose we would use split ptlock only for multi-threaded processes on
multi-cpu machines; but deciding that dynamically would have its own costs.
So for now enable it by config, at some number of cpus - since the Kconfig
language doesn't support inequalities, let preprocessor compare that with
NR_CPUS.  But I don't think it's worth being user-configurable: for good
testing of both split and unsplit configs, split now at 4 cpus, and perhaps
change that to 8 later.

There is a benefit even for singly threaded processes: kswapd can be attacking
one part of the mm while another part is busy faulting.

Signed-off-by: Hugh Dickins <hugh@veritas.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-10-29 21:40:42 -07:00
Hugh Dickins
69b0475456 [PATCH] mm: arm ready for split ptlock
Prepare arm for the split page_table_lock: three issues.

Signal handling's preserve and restore of iwmmxt context currently involves
reading and writing that context to and from user space, while holding
page_table_lock to secure the user page(s) against kswapd.  If we split the
lock, then the structure might span two pages, secured by to read into and
write from a kernel stack buffer, copying that out and in without locking (the
structure is 160 bytes in size, and here we're near the top of the kernel
stack).  Or would the overhead be noticeable?

arm_syscall's cmpxchg emulation use pte_offset_map_lock, instead of
pte_offset_map and mm-wide page_table_lock; and strictly, it should now also
take mmap_sem before descending to pmd, to guard against another thread
munmapping, and the page table pulled out beneath this thread.

Updated two comments in fault-armv.c.  adjust_pte is interesting, since its
modification of a pte in one part of the mm depends on the lock held when
calling update_mmu_cache for a pte in some other part of that mm.  This can't
be done with a split page_table_lock (and we've already taken the lowest lock
in the hierarchy here): so we'll have to disable split on arm, unless
CONFIG_CPU_CACHE_VIPT to ensures adjust_pte never used.

Signed-off-by: Hugh Dickins <hugh@veritas.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-10-29 21:40:42 -07:00
Hugh Dickins
b462705ac6 [PATCH] mm: arches skip ptlock
Convert those few architectures which are calling pud_alloc, pmd_alloc,
pte_alloc_map on a user mm, not to take the page_table_lock first, nor drop it
after.  Each of these can continue to use pte_alloc_map, no need to change
over to pte_alloc_map_lock, they're neither racy nor swappable.

In the sparc64 io_remap_pfn_range, flush_tlb_range then falls outside of the
page_table_lock: that's okay, on sparc64 it's like flush_tlb_mm, and that has
always been called from outside of page_table_lock in dup_mmap.

Signed-off-by: Hugh Dickins <hugh@veritas.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-10-29 21:40:40 -07:00
Hugh Dickins
872fec16d9 [PATCH] mm: init_mm without ptlock
First step in pushing down the page_table_lock.  init_mm.page_table_lock has
been used throughout the architectures (usually for ioremap): not to serialize
kernel address space allocation (that's usually vmlist_lock), but because
pud_alloc,pmd_alloc,pte_alloc_kernel expect caller holds it.

Reverse that: don't lock or unlock init_mm.page_table_lock in any of the
architectures; instead rely on pud_alloc,pmd_alloc,pte_alloc_kernel to take
and drop it when allocating a new one, to check lest a racing task already
did.  Similarly no page_table_lock in vmalloc's map_vm_area.

Some temporary ugliness in __pud_alloc and __pmd_alloc: since they also handle
user mms, which are converted only by a later patch, for now they have to lock
differently according to whether or not it's init_mm.

If sources get muddled, there's a danger that an arch source taking
init_mm.page_table_lock will be mixed with common source also taking it (or
neither take it).  So break the rules and make another change, which should
break the build for such a mismatch: remove the redundant mm arg from
pte_alloc_kernel (ppc64 scrapped its distinct ioremap_mm in 2.6.13).

Exceptions: arm26 used pte_alloc_kernel on user mm, now pte_alloc_map; ia64
used pte_alloc_map on init_mm, now pte_alloc_kernel; parisc had bad args to
pmd_alloc and pte_alloc_kernel in unused USE_HPPA_IOREMAP code; ppc64
map_io_page forgot to unlock on failure; ppc mmu_mapin_ram and ppc64 im_free
took page_table_lock for no good reason.

Signed-off-by: Hugh Dickins <hugh@veritas.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-10-29 21:40:40 -07:00
Nicolas Pitre
1a47ebc0d9 [ARM] 3059/1: fix XIP support
Patch from Nicolas Pitre

Fix XIP support after recent bootmem code refactoring.

Signed-off-by: Nicolas Pitre <nico@cam.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-29 16:28:29 +01:00
Linus Torvalds
83928e17b9 Merge master.kernel.org:/home/rmk/linux-2.6-arm
Minor manual fixups for gfp_t clashes.
2005-10-28 09:24:22 -07:00
Al Viro
f9e3214a79 [PATCH] gfp_t: dma-mapping (arm)
Signed-off-by: Al Viro <viro@zeniv.linux.org.uk>
Signed-off-by: Linus Torvalds <torvalds@osdl.org>
2005-10-28 08:16:47 -07:00
Deepak Saxena
0b7cd62ecd [ARM] 3017/1: Add support for 36-bit addresses to create_mapping()
Patch from Deepak Saxena

This patch adds support for 36-bit static mapped I/O. While there
are no platforms in the tree ATM that use it, it has been tested
tested on the IXP2350 NPU and I would like to get the support for
that chipset upstream one piece at a time. There are also other
Intel chipset ports in development that are waiting on this to go
upstream.

The patch replaces the print formats for physical addresses with
%016llx which will create a bit extraneous output on 32-bit systems,
but I think that is cleaner than having #ifdefs, specially since
users will only see the output in error cases.

Depends on 3016/1.

Signed-off-by: Deepak Saxena <dsaxena@plexity.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
2005-10-28 15:19:12 +01:00