/* * Driver for the Conexant CX23885 PCIe bridge * * Copyright (c) 2006 Steven Toth * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation; either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */ #include #include #include #include #include #include #include #include #include #include "btcx-risc.h" #include "cx23885-reg.h" #include "media/cx2341x.h" #include #include #define CX23885_VERSION_CODE KERNEL_VERSION(0, 0, 2) #define UNSET (-1U) #define CX23885_MAXBOARDS 8 /* Max number of inputs by card */ #define MAX_CX23885_INPUT 8 #define INPUT(nr) (&cx23885_boards[dev->board].input[nr]) #define RESOURCE_OVERLAY 1 #define RESOURCE_VIDEO 2 #define RESOURCE_VBI 4 #define BUFFER_TIMEOUT (HZ) /* 0.5 seconds */ #define CX23885_BOARD_NOAUTO UNSET #define CX23885_BOARD_UNKNOWN 0 #define CX23885_BOARD_HAUPPAUGE_HVR1800lp 1 #define CX23885_BOARD_HAUPPAUGE_HVR1800 2 #define CX23885_BOARD_HAUPPAUGE_HVR1250 3 #define CX23885_BOARD_DVICO_FUSIONHDTV_5_EXP 4 #define CX23885_BOARD_HAUPPAUGE_HVR1500Q 5 #define CX23885_BOARD_HAUPPAUGE_HVR1500 6 #define CX23885_BOARD_HAUPPAUGE_HVR1200 7 #define CX23885_BOARD_HAUPPAUGE_HVR1700 8 #define CX23885_BOARD_HAUPPAUGE_HVR1400 9 #define CX23885_BOARD_DVICO_FUSIONHDTV_7_DUAL_EXP 10 #define CX23885_BOARD_DVICO_FUSIONHDTV_DVB_T_DUAL_EXP 11 #define CX23885_BOARD_LEADTEK_WINFAST_PXDVR3200_H 12 #define CX23885_BOARD_COMPRO_VIDEOMATE_E650F 13 #define CX23885_BOARD_TBS_6920 14 #define CX23885_BOARD_TEVII_S470 15 #define CX23885_BOARD_DVBWORLD_2005 16 #define CX23885_BOARD_NETUP_DUAL_DVBS2_CI 17 #define CX23885_BOARD_HAUPPAUGE_HVR1270 18 #define CX23885_BOARD_HAUPPAUGE_HVR1275 19 #define CX23885_BOARD_HAUPPAUGE_HVR1255 20 #define CX23885_BOARD_HAUPPAUGE_HVR1210 21 #define CX23885_BOARD_MYGICA_X8506 22 #define CX23885_BOARD_MAGICPRO_PROHDTVE2 23 #define CX23885_BOARD_HAUPPAUGE_HVR1850 24 #define CX23885_BOARD_COMPRO_VIDEOMATE_E800 25 #define GPIO_0 0x00000001 #define GPIO_1 0x00000002 #define GPIO_2 0x00000004 #define GPIO_3 0x00000008 #define GPIO_4 0x00000010 #define GPIO_5 0x00000020 #define GPIO_6 0x00000040 #define GPIO_7 0x00000080 #define GPIO_8 0x00000100 #define GPIO_9 0x00000200 #define GPIO_10 0x00000400 #define GPIO_11 0x00000800 #define GPIO_12 0x00001000 #define GPIO_13 0x00002000 #define GPIO_14 0x00004000 #define GPIO_15 0x00008000 /* Currently unsupported by the driver: PAL/H, NTSC/Kr, SECAM B/G/H/LC */ #define CX23885_NORMS (\ V4L2_STD_NTSC_M | V4L2_STD_NTSC_M_JP | V4L2_STD_NTSC_443 | \ V4L2_STD_PAL_BG | V4L2_STD_PAL_DK | V4L2_STD_PAL_I | \ V4L2_STD_PAL_M | V4L2_STD_PAL_N | V4L2_STD_PAL_Nc | \ V4L2_STD_PAL_60 | V4L2_STD_SECAM_L | V4L2_STD_SECAM_DK) struct cx23885_fmt { char *name; u32 fourcc; /* v4l2 format id */ int depth; int flags; u32 cxformat; }; struct cx23885_ctrl { struct v4l2_queryctrl v; u32 off; u32 reg; u32 mask; u32 shift; }; struct cx23885_tvnorm { char *name; v4l2_std_id id; u32 cxiformat; u32 cxoformat; }; struct cx23885_fh { struct cx23885_dev *dev; enum v4l2_buf_type type; int radio; u32 resources; /* video overlay */ struct v4l2_window win; struct v4l2_clip *clips; unsigned int nclips; /* video capture */ struct cx23885_fmt *fmt; unsigned int width, height; /* vbi capture */ struct videobuf_queue vidq; struct videobuf_queue vbiq; /* MPEG Encoder specifics ONLY */ struct videobuf_queue mpegq; atomic_t v4l_reading; }; enum cx23885_itype { CX23885_VMUX_COMPOSITE1 = 1, CX23885_VMUX_COMPOSITE2, CX23885_VMUX_COMPOSITE3, CX23885_VMUX_COMPOSITE4, CX23885_VMUX_SVIDEO, CX23885_VMUX_TELEVISION, CX23885_VMUX_CABLE, CX23885_VMUX_DVB, CX23885_VMUX_DEBUG, CX23885_RADIO, }; enum cx23885_src_sel_type { CX23885_SRC_SEL_EXT_656_VIDEO = 0, CX23885_SRC_SEL_PARALLEL_MPEG_VIDEO }; /* buffer for one video frame */ struct cx23885_buffer { /* common v4l buffer stuff -- must be first */ struct videobuf_buffer vb; /* cx23885 specific */ unsigned int bpl; struct btcx_riscmem risc; struct cx23885_fmt *fmt; u32 count; }; struct cx23885_input { enum cx23885_itype type; unsigned int vmux; u32 gpio0, gpio1, gpio2, gpio3; }; typedef enum { CX23885_MPEG_UNDEFINED = 0, CX23885_MPEG_DVB, CX23885_ANALOG_VIDEO, CX23885_MPEG_ENCODER, } port_t; struct cx23885_board { char *name; port_t porta, portb, portc; unsigned int tuner_type; unsigned int radio_type; unsigned char tuner_addr; unsigned char radio_addr; /* Vendors can and do run the PCIe bridge at different * clock rates, driven physically by crystals on the PCBs. * The core has to accomodate this. This allows the user * to add new boards with new frequencys. The value is * expressed in Hz. * * The core framework will default this value based on * current designs, but it can vary. */ u32 clk_freq; struct cx23885_input input[MAX_CX23885_INPUT]; int cimax; /* for NetUP */ }; struct cx23885_subid { u16 subvendor; u16 subdevice; u32 card; }; struct cx23885_i2c { struct cx23885_dev *dev; int nr; /* i2c i/o */ struct i2c_adapter i2c_adap; struct i2c_algo_bit_data i2c_algo; struct i2c_client i2c_client; u32 i2c_rc; /* 885 registers used for raw addess */ u32 i2c_period; u32 reg_ctrl; u32 reg_stat; u32 reg_addr; u32 reg_rdata; u32 reg_wdata; }; struct cx23885_dmaqueue { struct list_head active; struct list_head queued; struct timer_list timeout; struct btcx_riscmem stopper; u32 count; }; struct cx23885_tsport { struct cx23885_dev *dev; int nr; int sram_chno; struct videobuf_dvb_frontends frontends; /* dma queues */ struct cx23885_dmaqueue mpegq; u32 ts_packet_size; u32 ts_packet_count; int width; int height; spinlock_t slock; /* registers */ u32 reg_gpcnt; u32 reg_gpcnt_ctl; u32 reg_dma_ctl; u32 reg_lngth; u32 reg_hw_sop_ctrl; u32 reg_gen_ctrl; u32 reg_bd_pkt_status; u32 reg_sop_status; u32 reg_fifo_ovfl_stat; u32 reg_vld_misc; u32 reg_ts_clk_en; u32 reg_ts_int_msk; u32 reg_ts_int_stat; u32 reg_src_sel; /* Default register vals */ int pci_irqmask; u32 dma_ctl_val; u32 ts_int_msk_val; u32 gen_ctrl_val; u32 ts_clk_en_val; u32 src_sel_val; u32 vld_misc_val; u32 hw_sop_ctrl_val; /* Allow a single tsport to have multiple frontends */ u32 num_frontends; void *port_priv; /* FIXME: temporary hack */ int (*set_frontend_save) (struct dvb_frontend *, struct dvb_frontend_parameters *); }; struct cx23885_dev { struct list_head devlist; atomic_t refcount; struct v4l2_device v4l2_dev; /* pci stuff */ struct pci_dev *pci; unsigned char pci_rev, pci_lat; int pci_bus, pci_slot; u32 __iomem *lmmio; u8 __iomem *bmmio; int pci_irqmask; int hwrevision; /* This valud is board specific and is used to configure the * AV core so we see nice clean and stable video and audio. */ u32 clk_freq; /* I2C adapters: Master 1 & 2 (External) & Master 3 (Internal only) */ struct cx23885_i2c i2c_bus[3]; int nr; struct mutex lock; struct mutex gpio_lock; /* board details */ unsigned int board; char name[32]; struct cx23885_tsport ts1, ts2; /* sram configuration */ struct sram_channel *sram_channels; enum { CX23885_BRIDGE_UNDEFINED = 0, CX23885_BRIDGE_885 = 885, CX23885_BRIDGE_887 = 887, CX23885_BRIDGE_888 = 888, } bridge; /* Analog video */ u32 resources; unsigned int input; u32 tvaudio; v4l2_std_id tvnorm; unsigned int tuner_type; unsigned char tuner_addr; unsigned int radio_type; unsigned char radio_addr; unsigned int has_radio; struct v4l2_subdev *sd_cx25840; struct v4l2_subdev *sd_ir; /* V4l */ u32 freq; struct video_device *video_dev; struct video_device *vbi_dev; struct video_device *radio_dev; struct cx23885_dmaqueue vidq; struct cx23885_dmaqueue vbiq; spinlock_t slock; /* MPEG Encoder ONLY settings */ u32 cx23417_mailbox; struct cx2341x_mpeg_params mpeg_params; struct video_device *v4l_device; atomic_t v4l_reader_count; struct cx23885_tvnorm encodernorm; }; static inline struct cx23885_dev *to_cx23885(struct v4l2_device *v4l2_dev) { return container_of(v4l2_dev, struct cx23885_dev, v4l2_dev); } #define call_all(dev, o, f, args...) \ v4l2_device_call_all(&dev->v4l2_dev, 0, o, f, ##args) #define CX23885_HW_888_IR (1 << 0) #define call_hw(dev, grpid, o, f, args...) \ v4l2_device_call_all(&dev->v4l2_dev, grpid, o, f, ##args) extern struct v4l2_subdev *cx23885_find_hw(struct cx23885_dev *dev, u32 hw); extern struct list_head cx23885_devlist; #define SRAM_CH01 0 /* Video A */ #define SRAM_CH02 1 /* VBI A */ #define SRAM_CH03 2 /* Video B */ #define SRAM_CH04 3 /* Transport via B */ #define SRAM_CH05 4 /* VBI B */ #define SRAM_CH06 5 /* Video C */ #define SRAM_CH07 6 /* Transport via C */ #define SRAM_CH08 7 /* Audio Internal A */ #define SRAM_CH09 8 /* Audio Internal B */ #define SRAM_CH10 9 /* Audio External */ #define SRAM_CH11 10 /* COMB_3D_N */ #define SRAM_CH12 11 /* Comb 3D N1 */ #define SRAM_CH13 12 /* Comb 3D N2 */ #define SRAM_CH14 13 /* MOE Vid */ #define SRAM_CH15 14 /* MOE RSLT */ struct sram_channel { char *name; u32 cmds_start; u32 ctrl_start; u32 cdt; u32 fifo_start; u32 fifo_size; u32 ptr1_reg; u32 ptr2_reg; u32 cnt1_reg; u32 cnt2_reg; u32 jumponly; }; /* ----------------------------------------------------------- */ #define cx_read(reg) readl(dev->lmmio + ((reg)>>2)) #define cx_write(reg, value) writel((value), dev->lmmio + ((reg)>>2)) #define cx_andor(reg, mask, value) \ writel((readl(dev->lmmio+((reg)>>2)) & ~(mask)) |\ ((value) & (mask)), dev->lmmio+((reg)>>2)) #define cx_set(reg, bit) cx_andor((reg), (bit), (bit)) #define cx_clear(reg, bit) cx_andor((reg), (bit), 0) /* ----------------------------------------------------------- */ /* cx23885-core.c */ extern int cx23885_sram_channel_setup(struct cx23885_dev *dev, struct sram_channel *ch, unsigned int bpl, u32 risc); extern void cx23885_sram_channel_dump(struct cx23885_dev *dev, struct sram_channel *ch); extern int cx23885_risc_stopper(struct pci_dev *pci, struct btcx_riscmem *risc, u32 reg, u32 mask, u32 value); extern int cx23885_risc_buffer(struct pci_dev *pci, struct btcx_riscmem *risc, struct scatterlist *sglist, unsigned int top_offset, unsigned int bottom_offset, unsigned int bpl, unsigned int padding, unsigned int lines); void cx23885_cancel_buffers(struct cx23885_tsport *port); extern int cx23885_restart_queue(struct cx23885_tsport *port, struct cx23885_dmaqueue *q); extern void cx23885_wakeup(struct cx23885_tsport *port, struct cx23885_dmaqueue *q, u32 count); extern void cx23885_gpio_set(struct cx23885_dev *dev, u32 mask); extern void cx23885_gpio_clear(struct cx23885_dev *dev, u32 mask); extern void cx23885_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput); /* ----------------------------------------------------------- */ /* cx23885-cards.c */ extern struct cx23885_board cx23885_boards[]; extern const unsigned int cx23885_bcount; extern struct cx23885_subid cx23885_subids[]; extern const unsigned int cx23885_idcount; extern int cx23885_tuner_callback(void *priv, int component, int command, int arg); extern void cx23885_card_list(struct cx23885_dev *dev); extern int cx23885_ir_init(struct cx23885_dev *dev); extern void cx23885_gpio_setup(struct cx23885_dev *dev); extern void cx23885_card_setup(struct cx23885_dev *dev); extern void cx23885_card_setup_pre_i2c(struct cx23885_dev *dev); extern int cx23885_dvb_register(struct cx23885_tsport *port); extern int cx23885_dvb_unregister(struct cx23885_tsport *port); extern int cx23885_buf_prepare(struct videobuf_queue *q, struct cx23885_tsport *port, struct cx23885_buffer *buf, enum v4l2_field field); extern void cx23885_buf_queue(struct cx23885_tsport *port, struct cx23885_buffer *buf); extern void cx23885_free_buffer(struct videobuf_queue *q, struct cx23885_buffer *buf); /* ----------------------------------------------------------- */ /* cx23885-video.c */ /* Video */ extern int cx23885_video_register(struct cx23885_dev *dev); extern void cx23885_video_unregister(struct cx23885_dev *dev); extern int cx23885_video_irq(struct cx23885_dev *dev, u32 status); /* ----------------------------------------------------------- */ /* cx23885-vbi.c */ extern int cx23885_vbi_fmt(struct file *file, void *priv, struct v4l2_format *f); extern void cx23885_vbi_timeout(unsigned long data); extern struct videobuf_queue_ops cx23885_vbi_qops; /* cx23885-i2c.c */ extern int cx23885_i2c_register(struct cx23885_i2c *bus); extern int cx23885_i2c_unregister(struct cx23885_i2c *bus); extern void cx23885_av_clk(struct cx23885_dev *dev, int enable); /* ----------------------------------------------------------- */ /* cx23885-417.c */ extern int cx23885_417_register(struct cx23885_dev *dev); extern void cx23885_417_unregister(struct cx23885_dev *dev); extern int cx23885_irq_417(struct cx23885_dev *dev, u32 status); extern void cx23885_417_check_encoder(struct cx23885_dev *dev); extern void cx23885_mc417_init(struct cx23885_dev *dev); extern int mc417_memory_read(struct cx23885_dev *dev, u32 address, u32 *value); extern int mc417_memory_write(struct cx23885_dev *dev, u32 address, u32 value); extern int mc417_register_read(struct cx23885_dev *dev, u16 address, u32 *value); extern int mc417_register_write(struct cx23885_dev *dev, u16 address, u32 value); extern void mc417_gpio_set(struct cx23885_dev *dev, u32 mask); extern void mc417_gpio_clear(struct cx23885_dev *dev, u32 mask); extern void mc417_gpio_enable(struct cx23885_dev *dev, u32 mask, int asoutput); /* ----------------------------------------------------------- */ /* tv norms */ static inline unsigned int norm_maxw(v4l2_std_id norm) { return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 720 : 768; } static inline unsigned int norm_maxh(v4l2_std_id norm) { return (norm & V4L2_STD_625_50) ? 576 : 480; } static inline unsigned int norm_swidth(v4l2_std_id norm) { return (norm & (V4L2_STD_MN & ~V4L2_STD_PAL_Nc)) ? 754 : 922; }