590aad8835
[ Upstream commit bcc44f6b74106b31f0b0408b70305a40360d63b7 ]
There is no VIA2 chip on the Mac IIfx, so don't call via_flush_cache().
This avoids a boot crash which appeared in v5.4.
printk: console [ttyS0] enabled
printk: bootconsole [debug0] disabled
printk: bootconsole [debug0] disabled
Calibrating delay loop... 9.61 BogoMIPS (lpj=48064)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes, linear)
devtmpfs: initialized
random: get_random_u32 called from bucket_table_alloc.isra.27+0x68/0x194 with crng_init=0
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 19112604462750000 ns
futex hash table entries: 256 (order: -1, 3072 bytes, linear)
NET: Registered protocol family 16
Data read fault at 0x00000000 in Super Data (pc=0x8a6a)
BAD KERNEL BUSERR
Oops: 00000000
Modules linked in:
PC: [<00008a6a>] via_flush_cache+0x12/0x2c
SR: 2700 SP: 01c1fe3c a2: 01c24000
d0: 00001119 d1: 0000000c d2: 00012000 d3: 0000000f
d4: 01c06840 d5: 00033b92 a0: 00000000 a1: 00000000
Process swapper (pid: 1, task=01c24000)
Frame format=B ssw=0755 isc=0200 isb=fff7 daddr=00000000 dobuf=01c1fed0
baddr=00008a6e dibuf=0000004e ver=f
Stack from 01c1fec4:
01c1fed0 00007d7e 00010080 01c1fedc 0000792e 00000001 01c1fef4 00006b40
01c80000 00040000 00000006 00000003 01c1ff1c 004a545e 004ff200 00040000
00000000 00000003 01c06840 00033b92 004a5410 004b6c88 01c1ff84 000021e2
00000073 00000003 01c06840 00033b92 0038507a 004bb094 004b6ca8 004b6c88
004b6ca4 004b6c88 000021ae 00020002 00000000 01c0685d 00000000 01c1ffb4
0049f938 00409c85 01c06840 0045bd40 00000073 00000002 00000002 00000000
Call Trace: [<00007d7e>] mac_cache_card_flush+0x12/0x1c
[<00010080>] fix_dnrm+0x2/0x18
[<0000792e>] cache_push+0x46/0x5a
[<00006b40>] arch_dma_prep_coherent+0x60/0x6e
[<00040000>] switched_to_dl+0x76/0xd0
[<004a545e>] dma_atomic_pool_init+0x4e/0x188
[<00040000>] switched_to_dl+0x76/0xd0
[<00033b92>] parse_args+0x0/0x370
[<004a5410>] dma_atomic_pool_init+0x0/0x188
[<000021e2>] do_one_initcall+0x34/0x1be
[<00033b92>] parse_args+0x0/0x370
[<0038507a>] strcpy+0x0/0x1e
[<000021ae>] do_one_initcall+0x0/0x1be
[<00020002>] do_proc_dointvec_conv+0x54/0x74
[<0049f938>] kernel_init_freeable+0x126/0x190
[<0049f94c>] kernel_init_freeable+0x13a/0x190
[<004a5410>] dma_atomic_pool_init+0x0/0x188
[<00041798>] complete+0x0/0x3c
[<000b9b0c>] kfree+0x0/0x20a
[<0038df98>] schedule+0x0/0xd0
[<0038d604>] kernel_init+0x0/0xda
[<0038d610>] kernel_init+0xc/0xda
[<0038d604>] kernel_init+0x0/0xda
[<00002d38>] ret_from_kernel_thread+0xc/0x14
Code: 0000 2079 0048 10da 2279 0048 10c8 d3c8 <1011> 0200 fff7 1280 d1f9 0048 10c8 1010 0000 0008 1080 4e5e 4e75 4e56 0000 2039
Disabling lock debugging due to kernel taint
Kernel panic - not syncing: Attempted to kill init! exitcode=0x0000000b
Thanks to Stan Johnson for capturing the console log and running git
bisect.
Git bisect said commit 8e3a68fb55 ("dma-mapping: make
dma_atomic_pool_init self-contained") is the first "bad" commit. I don't
know why. Perhaps mach_l2_flush first became reachable with that commit.
Fixes: 1da177e4c3 ("Linux-2.6.12-rc2")
Reported-and-tested-by: Stan Johnson <userm57@yahoo.com>
Signed-off-by: Finn Thain <fthain@telegraphics.com.au>
Cc: Joshua Thompson <funaho@jurai.org>
Link: https://lore.kernel.org/r/b8bbeef197d6b3898e82ed0d231ad08f575a4b34.1589949122.git.fthain@telegraphics.com.au
Signed-off-by: Geert Uytterhoeven <geert@linux-m68k.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
281 lines
11 KiB
C
281 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* 6522 Versatile Interface Adapter (VIA)
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*
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* There are two of these on the Mac II. Some IRQ's are vectored
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* via them as are assorted bits and bobs - eg rtc, adb. The picture
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* is a bit incomplete as the Mac documentation doesn't cover this well
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*/
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#ifndef _ASM_MAC_VIA_H_
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#define _ASM_MAC_VIA_H_
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/*
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* Base addresses for the VIAs. There are two in every machine,
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* although on some machines the second is an RBV or an OSS.
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* The OSS is different enough that it's handled separately.
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*
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* Do not use these values directly; use the via1 and via2 variables
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* instead (and don't forget to check rbv_present when using via2!)
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*/
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#define VIA1_BASE (0x50F00000)
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#define VIA2_BASE (0x50F02000)
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#define RBV_BASE (0x50F26000)
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/*
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* Not all of these are true post MacII I think.
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* CSA: probably the ones CHRP marks as 'unused' change purposes
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* when the IWM becomes the SWIM.
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* http://www.rs6000.ibm.com/resource/technology/chrpio/via5.mak.html
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* ftp://ftp.austin.ibm.com/pub/technology/spec/chrp/inwork/CHRP_IORef_1.0.pdf
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*
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* also, http://developer.apple.com/technotes/hw/hw_09.html claims the
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* following changes for IIfx:
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* VIA1A_vSccWrReq not available and that VIA1A_vSync has moved to an IOP.
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* Also, "All of the functionality of VIA2 has been moved to other chips".
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*/
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#define VIA1A_vSccWrReq 0x80 /* SCC write. (input)
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* [CHRP] SCC WREQ: Reflects the state of the
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* Wait/Request pins from the SCC.
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* [Macintosh Family Hardware]
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* as CHRP on SE/30,II,IIx,IIcx,IIci.
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* on IIfx, "0 means an active request"
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*/
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#define VIA1A_vRev8 0x40 /* Revision 8 board ???
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* [CHRP] En WaitReqB: Lets the WaitReq_L
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* signal from port B of the SCC appear on
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* the PA7 input pin. Output.
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* [Macintosh Family] On the SE/30, this
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* is the bit to flip screen buffers.
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* 0=alternate, 1=main.
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* on II,IIx,IIcx,IIci,IIfx this is a bit
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* for Rev ID. 0=II,IIx, 1=IIcx,IIci,IIfx
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*/
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#define VIA1A_vHeadSel 0x20 /* Head select for IWM.
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* [CHRP] unused.
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* [Macintosh Family] "Floppy disk
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* state-control line SEL" on all but IIfx
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*/
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#define VIA1A_vOverlay 0x10 /* [Macintosh Family] On SE/30,II,IIx,IIcx
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* this bit enables the "Overlay" address
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* map in the address decoders as it is on
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* reset for mapping the ROM over the reset
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* vector. 1=use overlay map.
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* On the IIci,IIfx it is another bit of the
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* CPU ID: 0=normal IIci, 1=IIci with parity
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* feature or IIfx.
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* [CHRP] En WaitReqA: Lets the WaitReq_L
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* signal from port A of the SCC appear
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* on the PA7 input pin (CHRP). Output.
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* [MkLinux] "Drive Select"
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* (with 0x20 being 'disk head select')
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*/
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#define VIA1A_vSync 0x08 /* [CHRP] Sync Modem: modem clock select:
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* 1: select the external serial clock to
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* drive the SCC's /RTxCA pin.
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* 0: Select the 3.6864MHz clock to drive
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* the SCC cell.
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* [Macintosh Family] Correct on all but IIfx
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*/
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/* Macintosh Family Hardware sez: bits 0-2 of VIA1A are volume control
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* on Macs which had the PWM sound hardware. Reserved on newer models.
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* On IIci,IIfx, bits 1-2 are the rest of the CPU ID:
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* bit 2: 1=IIci, 0=IIfx
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* bit 1: 1 on both IIci and IIfx.
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* MkLinux sez bit 0 is 'burnin flag' in this case.
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* CHRP sez: VIA1A bits 0-2 and 5 are 'unused': if programmed as
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* inputs, these bits will read 0.
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*/
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#define VIA1A_vVolume 0x07 /* Audio volume mask for PWM */
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#define VIA1A_CPUID0 0x02 /* CPU id bit 0 on RBV, others */
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#define VIA1A_CPUID1 0x04 /* CPU id bit 0 on RBV, others */
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#define VIA1A_CPUID2 0x10 /* CPU id bit 0 on RBV, others */
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#define VIA1A_CPUID3 0x40 /* CPU id bit 0 on RBV, others */
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/* Info on VIA1B is from Macintosh Family Hardware & MkLinux.
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* CHRP offers no info. */
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#define VIA1B_vSound 0x80 /* Sound enable (for compatibility with
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* PWM hardware) 0=enabled.
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* Also, on IIci w/parity, shows parity error
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* 0=error, 1=OK. */
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#define VIA1B_vMystery 0x40 /* On IIci, parity enable. 0=enabled,1=disabled
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* On SE/30, vertical sync interrupt enable.
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* 0=enabled. This vSync interrupt shows up
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* as a slot $E interrupt. */
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#define VIA1B_vADBS2 0x20 /* ADB state input bit 1 (unused on IIfx) */
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#define VIA1B_vADBS1 0x10 /* ADB state input bit 0 (unused on IIfx) */
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#define VIA1B_vADBInt 0x08 /* ADB interrupt 0=interrupt (unused on IIfx)*/
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#define VIA1B_vRTCEnb 0x04 /* Enable Real time clock. 0=enabled. */
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#define VIA1B_vRTCClk 0x02 /* Real time clock serial-clock line. */
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#define VIA1B_vRTCData 0x01 /* Real time clock serial-data line. */
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/* MkLinux defines the following "VIA1 Register B contents where they
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* differ from standard VIA1". From the naming scheme, we assume they
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* correspond to a VIA work-alike named 'EVR'. */
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#define EVRB_XCVR 0x08 /* XCVR_SESSION* */
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#define EVRB_FULL 0x10 /* VIA_FULL */
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#define EVRB_SYSES 0x20 /* SYS_SESSION */
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#define EVRB_AUXIE 0x00 /* Enable A/UX Interrupt Scheme */
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#define EVRB_AUXID 0x40 /* Disable A/UX Interrupt Scheme */
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#define EVRB_SFTWRIE 0x00 /* Software Interrupt ReQuest */
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#define EVRB_SFTWRID 0x80 /* Software Interrupt ReQuest */
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/*
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* VIA2 A register is the interrupt lines raised off the nubus
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* slots.
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* The below info is from 'Macintosh Family Hardware.'
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* MkLinux calls the 'IIci internal video IRQ' below the 'RBV slot 0 irq.'
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* It also notes that the slot $9 IRQ is the 'Ethernet IRQ' and
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* defines the 'Video IRQ' as 0x40 for the 'EVR' VIA work-alike.
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* Perhaps OSS uses vRAM1 and vRAM2 for ADB.
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*/
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#define VIA2A_vRAM1 0x80 /* RAM size bit 1 (IIci: reserved) */
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#define VIA2A_vRAM0 0x40 /* RAM size bit 0 (IIci: internal video IRQ) */
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#define VIA2A_vIRQE 0x20 /* IRQ from slot $E */
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#define VIA2A_vIRQD 0x10 /* IRQ from slot $D */
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#define VIA2A_vIRQC 0x08 /* IRQ from slot $C */
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#define VIA2A_vIRQB 0x04 /* IRQ from slot $B */
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#define VIA2A_vIRQA 0x02 /* IRQ from slot $A */
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#define VIA2A_vIRQ9 0x01 /* IRQ from slot $9 */
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/* RAM size bits decoded as follows:
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* bit1 bit0 size of ICs in bank A
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* 0 0 256 kbit
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* 0 1 1 Mbit
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* 1 0 4 Mbit
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* 1 1 16 Mbit
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*/
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/*
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* Register B has the fun stuff in it
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*/
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#define VIA2B_vVBL 0x80 /* VBL output to VIA1 (60.15Hz) driven by
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* timer T1.
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* on IIci, parity test: 0=test mode.
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* [MkLinux] RBV_PARODD: 1=odd,0=even. */
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#define VIA2B_vSndJck 0x40 /* External sound jack status.
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* 0=plug is inserted. On SE/30, always 0 */
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#define VIA2B_vTfr0 0x20 /* Transfer mode bit 0 ack from NuBus */
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#define VIA2B_vTfr1 0x10 /* Transfer mode bit 1 ack from NuBus */
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#define VIA2B_vMode32 0x08 /* 24/32bit switch - doubles as cache flush
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* on II, AMU/PMMU control.
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* if AMU, 0=24bit to 32bit translation
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* if PMMU, 1=PMMU is accessing page table.
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* on SE/30 tied low.
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* on IIx,IIcx,IIfx, unused.
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* on IIci/RBV, cache control. 0=flush cache.
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*/
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#define VIA2B_vPower 0x04 /* Power off, 0=shut off power.
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* on SE/30 this signal sent to PDS card. */
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#define VIA2B_vBusLk 0x02 /* Lock NuBus transactions, 0=locked.
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* on SE/30 sent to PDS card. */
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#define VIA2B_vCDis 0x01 /* Cache control. On IIci, 1=disable cache card
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* on others, 0=disable processor's instruction
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* and data caches. */
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/* Apple sez: http://developer.apple.com/technotes/ov/ov_04.html
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* Another example of a valid function that has no ROM support is the use
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* of the alternate video page for page-flipping animation. Since there
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* is no ROM call to flip pages, it is necessary to go play with the
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* right bit in the VIA chip (6522 Versatile Interface Adapter).
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* [CSA: don't know which one this is, but it's one of 'em!]
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*/
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/*
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* 6522 registers - see databook.
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* CSA: Assignments for VIA1 confirmed from CHRP spec.
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*/
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/* partial address decode. 0xYYXX : XX part for RBV, YY part for VIA */
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/* Note: 15 VIA regs, 8 RBV regs */
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#define vBufB 0x0000 /* [VIA/RBV] Register B */
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#define vBufAH 0x0200 /* [VIA only] Buffer A, with handshake. DON'T USE! */
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#define vDirB 0x0400 /* [VIA only] Data Direction Register B. */
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#define vDirA 0x0600 /* [VIA only] Data Direction Register A. */
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#define vT1CL 0x0800 /* [VIA only] Timer one counter low. */
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#define vT1CH 0x0a00 /* [VIA only] Timer one counter high. */
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#define vT1LL 0x0c00 /* [VIA only] Timer one latches low. */
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#define vT1LH 0x0e00 /* [VIA only] Timer one latches high. */
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#define vT2CL 0x1000 /* [VIA only] Timer two counter low. */
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#define vT2CH 0x1200 /* [VIA only] Timer two counter high. */
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#define vSR 0x1400 /* [VIA only] Shift register. */
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#define vACR 0x1600 /* [VIA only] Auxiliary control register. */
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#define vPCR 0x1800 /* [VIA only] Peripheral control register. */
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/* CHRP sez never ever to *write* this.
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* Mac family says never to *change* this.
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* In fact we need to initialize it once at start. */
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#define vIFR 0x1a00 /* [VIA/RBV] Interrupt flag register. */
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#define vIER 0x1c00 /* [VIA/RBV] Interrupt enable register. */
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#define vBufA 0x1e00 /* [VIA/RBV] register A (no handshake) */
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/* The RBV only decodes the bottom eight address lines; the VIA doesn't
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* decode the bottom eight -- so vBufB | rBufB will always get you BufB */
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/* CSA: in fact, only bits 0,1, and 4 seem to be decoded.
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* BUT note the values for rIER and rIFR, where the top 8 bits *do* seem
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* to matter. In fact *all* of the top 8 bits seem to matter;
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* setting rIER=0x1813 and rIFR=0x1803 doesn't work, either.
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* Perhaps some sort of 'compatibility mode' is built-in? [21-May-1999]
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*/
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#define rBufB 0x0000 /* [VIA/RBV] Register B */
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#define rExp 0x0001 /* [RBV only] RBV future expansion (always 0) */
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#define rSIFR 0x0002 /* [RBV only] RBV slot interrupts register. */
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#define rIFR 0x1a03 /* [VIA/RBV] RBV interrupt flag register. */
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#define rMonP 0x0010 /* [RBV only] RBV video monitor type. */
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#define rChpT 0x0011 /* [RBV only] RBV test mode register (reads as 0). */
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#define rSIER 0x0012 /* [RBV only] RBV slot interrupt enables. */
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#define rIER 0x1c13 /* [VIA/RBV] RBV interrupt flag enable register. */
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#define rBufA rSIFR /* the 'slot interrupts register' is BufA on a VIA */
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/*
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* Video monitor parameters, for rMonP:
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*/
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#define RBV_DEPTH 0x07 /* bits per pixel: 000=1,001=2,010=4,011=8 */
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#define RBV_MONID 0x38 /* monitor type, as below. */
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#define RBV_VIDOFF 0x40 /* 1 turns off onboard video */
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/* Supported monitor types: */
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#define MON_15BW (1<<3) /* 15" BW portrait. */
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#define MON_IIGS (2<<3) /* 12" color (modified IIGS monitor). */
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#define MON_15RGB (5<<3) /* 15" RGB portrait. */
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#define MON_12OR13 (6<<3) /* 12" BW or 13" RGB. */
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#define MON_NONE (7<<3) /* No monitor attached. */
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/* To clarify IER manipulations */
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#define IER_SET_BIT(b) (0x80 | (1<<(b)) )
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#define IER_CLR_BIT(b) (0x7F & (1<<(b)) )
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#ifndef __ASSEMBLY__
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extern volatile __u8 *via1,*via2;
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extern int rbv_present,via_alt_mapping;
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struct irq_desc;
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extern void via_l2_flush(int writeback);
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extern void via_register_interrupts(void);
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extern void via_irq_enable(int);
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extern void via_irq_disable(int);
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extern void via_nubus_irq_startup(int irq);
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extern void via_nubus_irq_shutdown(int irq);
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extern void via1_irq(struct irq_desc *desc);
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extern void via1_set_head(int);
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extern int via2_scsi_drq_pending(void);
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static inline int rbv_set_video_bpp(int bpp)
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{
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char val = (bpp==1)?0:(bpp==2)?1:(bpp==4)?2:(bpp==8)?3:-1;
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if (!rbv_present || val<0) return -1;
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via2[rMonP] = (via2[rMonP] & ~RBV_DEPTH) | val;
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return 0;
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}
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#endif /* __ASSEMBLY__ */
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#endif /* _ASM_MAC_VIA_H_ */
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