2c44110300
commit 25ab14cbe9d1b66fda44c71a2db7582a31b6f5cd upstream.
Remove the inline asm with a DIVU instruction from `__div64_32' and use
plain C code for the intended DIVMOD calculation instead. GCC is smart
enough to know that both the quotient and the remainder are calculated
with single DIVU, so with ISAs up to R5 the same instruction is actually
produced with overall similar code.
For R6 compiled code will work, but separate DIVU and MODU instructions
will be produced, which are also interlocked, so scalar implementations
will likely not perform as well as older ISAs with their asynchronous MD
unit. Likely still faster then the generic algorithm though.
This removes a compilation error for R6 however where the original DIVU
instruction is not supported anymore and the MDU accumulator registers
have been removed and consequently GCC complains as to a constraint it
cannot find a register for:
In file included from ./include/linux/math.h:5,
from ./include/linux/kernel.h:13,
from mm/page-writeback.c:15:
./include/linux/math64.h: In function 'div_u64_rem':
./arch/mips/include/asm/div64.h:76:17: error: inconsistent operand constraints in an 'asm'
76 | __asm__("divu $0, %z1, %z2" \
| ^~~~~~~
./include/asm-generic/div64.h:245:25: note: in expansion of macro '__div64_32'
245 | __rem = __div64_32(&(n), __base); \
| ^~~~~~~~~~
./include/linux/math64.h:91:22: note: in expansion of macro 'do_div'
91 | *remainder = do_div(dividend, divisor);
| ^~~~~~
This has passed correctness verification with test_div64 and reduced the
module's average execution time down to 1.0404s from 1.0445s with R3400
@40MHz. The module's MIPS I machine code has also shrunk by 12 bytes or
3 instructions.
Signed-off-by: Maciej W. Rozycki <macro@orcam.me.uk>
Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
92 lines
2.2 KiB
C
92 lines
2.2 KiB
C
/*
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* Copyright (C) 2000, 2004, 2021 Maciej W. Rozycki
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* Copyright (C) 2003, 07 Ralf Baechle (ralf@linux-mips.org)
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#ifndef __ASM_DIV64_H
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#define __ASM_DIV64_H
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#include <asm/bitsperlong.h>
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#if BITS_PER_LONG == 32
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/*
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* No traps on overflows for any of these...
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*/
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#define do_div64_32(res, high, low, base) ({ \
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unsigned long __cf, __tmp, __tmp2, __i; \
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unsigned long __quot32, __mod32; \
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\
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__asm__( \
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" .set push \n" \
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" .set noat \n" \
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" .set noreorder \n" \
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" move %2, $0 \n" \
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" move %3, $0 \n" \
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" b 1f \n" \
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" li %4, 0x21 \n" \
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"0: \n" \
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" sll $1, %0, 0x1 \n" \
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" srl %3, %0, 0x1f \n" \
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" or %0, $1, %5 \n" \
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" sll %1, %1, 0x1 \n" \
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" sll %2, %2, 0x1 \n" \
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"1: \n" \
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" bnez %3, 2f \n" \
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" sltu %5, %0, %z6 \n" \
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" bnez %5, 3f \n" \
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"2: \n" \
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" addiu %4, %4, -1 \n" \
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" subu %0, %0, %z6 \n" \
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" addiu %2, %2, 1 \n" \
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"3: \n" \
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" bnez %4, 0b \n" \
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" srl %5, %1, 0x1f \n" \
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" .set pop" \
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: "=&r" (__mod32), "=&r" (__tmp), \
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"=&r" (__quot32), "=&r" (__cf), \
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"=&r" (__i), "=&r" (__tmp2) \
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: "Jr" (base), "0" (high), "1" (low)); \
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\
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(res) = __quot32; \
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__mod32; \
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})
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#define __div64_32(n, base) ({ \
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unsigned long __upper, __low, __high, __radix; \
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unsigned long long __quot; \
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unsigned long long __div; \
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unsigned long __mod; \
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\
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__div = (*n); \
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__radix = (base); \
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\
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__high = __div >> 32; \
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__low = __div; \
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\
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if (__high < __radix) { \
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__upper = __high; \
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__high = 0; \
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} else { \
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__upper = __high % __radix; \
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__high /= __radix; \
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} \
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\
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__mod = do_div64_32(__low, __upper, __low, __radix); \
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\
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__quot = __high; \
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__quot = __quot << 32 | __low; \
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(*n) = __quot; \
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__mod; \
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})
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#endif /* BITS_PER_LONG == 32 */
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#include <asm-generic/div64.h>
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#endif /* __ASM_DIV64_H */
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