c24a8a7a99
Add MSI chip and MSIX chip definitions. For MSI, we map the link interrupt to a MSI link IRQ which will do a second level of dispatch based on the MSI status register. The MSI chip definitions use the MSI enable register to enable and disable the MSI irqs. For MSI-X, we split the 32 available MSI-X vectors across the four PCIe links (8 each). These PIC interrupts generate an IRQ per link which uses a second level dispatch as well. The MSI-X chip definition uses the standard functions to enable and disable interrupts. Signed-off-by: Jayachandran C <jchandra@broadcom.com> Signed-off-by: John Crispin <blogic@openwrt.org> Patchwork: http://patchwork.linux-mips.org/patch/6270/
18 lines
477 B
C
18 lines
477 B
C
/*
|
|
* This file is subject to the terms and conditions of the GNU General Public
|
|
* License. See the file "COPYING" in the main directory of this archive
|
|
* for more details.
|
|
*
|
|
* Copyright (C) 2011 Netlogic Microsystems.
|
|
*/
|
|
#ifndef __ASM_NETLOGIC_IRQ_H
|
|
#define __ASM_NETLOGIC_IRQ_H
|
|
|
|
#include <asm/mach-netlogic/multi-node.h>
|
|
#define NLM_IRQS_PER_NODE 1024
|
|
#define NR_IRQS (NLM_IRQS_PER_NODE * NLM_NR_NODES)
|
|
|
|
#define MIPS_CPU_IRQ_BASE 0
|
|
|
|
#endif /* __ASM_NETLOGIC_IRQ_H */
|