41173abc57
Based on 1 normalized pattern(s): this program is free software you can distribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is distributed in the hope it will be useful but without any warranty without even the implied warranty of merchantability or fitness for a particular purpose see the gnu general public license for more details you should have received a copy of the gnu general public license along with this program if not write to the free software foundation inc 59 temple place suite 330 boston ma 02111 1307 usa extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 32 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Reviewed-by: Richard Fontana <rfontana@redhat.com> Reviewed-by: Steve Winslow <swinslow@gmail.com> Reviewed-by: Alexios Zavras <alexios.zavras@intel.com> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190528170026.531157061@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
135 lines
3.3 KiB
C
135 lines
3.3 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (C) 1999, 2000, 2004, 2005 MIPS Technologies, Inc.
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* All rights reserved.
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* Authors: Carsten Langgaard <carstenl@mips.com>
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* Maciej W. Rozycki <macro@mips.com>
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* Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
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*
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* MIPS boards specific PCI support.
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*/
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <asm/mips-boards/msc01_pci.h>
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#define PCI_ACCESS_READ 0
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#define PCI_ACCESS_WRITE 1
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/*
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* PCI configuration cycle AD bus definition
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*/
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/* Type 0 */
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#define PCI_CFG_TYPE0_REG_SHF 0
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#define PCI_CFG_TYPE0_FUNC_SHF 8
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/* Type 1 */
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#define PCI_CFG_TYPE1_REG_SHF 0
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#define PCI_CFG_TYPE1_FUNC_SHF 8
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#define PCI_CFG_TYPE1_DEV_SHF 11
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#define PCI_CFG_TYPE1_BUS_SHF 16
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static int msc_pcibios_config_access(unsigned char access_type,
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struct pci_bus *bus, unsigned int devfn, int where, u32 * data)
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{
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unsigned char busnum = bus->number;
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u32 intr;
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/* Clear status register bits. */
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MSC_WRITE(MSC01_PCI_INTSTAT,
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(MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT));
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MSC_WRITE(MSC01_PCI_CFGADDR,
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((busnum << MSC01_PCI_CFGADDR_BNUM_SHF) |
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(PCI_SLOT(devfn) << MSC01_PCI_CFGADDR_DNUM_SHF) |
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(PCI_FUNC(devfn) << MSC01_PCI_CFGADDR_FNUM_SHF) |
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((where / 4) << MSC01_PCI_CFGADDR_RNUM_SHF)));
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/* Perform access */
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if (access_type == PCI_ACCESS_WRITE)
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MSC_WRITE(MSC01_PCI_CFGDATA, *data);
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else
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MSC_READ(MSC01_PCI_CFGDATA, *data);
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/* Detect Master/Target abort */
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MSC_READ(MSC01_PCI_INTSTAT, intr);
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if (intr & (MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT)) {
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/* Error occurred */
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/* Clear bits */
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MSC_WRITE(MSC01_PCI_INTSTAT,
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(MSC01_PCI_INTCFG_MA_BIT | MSC01_PCI_INTCFG_TA_BIT));
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return -1;
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}
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return 0;
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}
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/*
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* We can't address 8 and 16 bit words directly. Instead we have to
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* read/write a 32bit word and mask/modify the data we actually want.
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*/
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static int msc_pcibios_read(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 * val)
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{
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u32 data = 0;
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if ((size == 2) && (where & 1))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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else if ((size == 4) && (where & 3))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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if (msc_pcibios_config_access(PCI_ACCESS_READ, bus, devfn, where,
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&data))
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return -1;
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if (size == 1)
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*val = (data >> ((where & 3) << 3)) & 0xff;
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else if (size == 2)
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*val = (data >> ((where & 3) << 3)) & 0xffff;
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else
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*val = data;
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return PCIBIOS_SUCCESSFUL;
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}
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static int msc_pcibios_write(struct pci_bus *bus, unsigned int devfn,
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int where, int size, u32 val)
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{
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u32 data = 0;
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if ((size == 2) && (where & 1))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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else if ((size == 4) && (where & 3))
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return PCIBIOS_BAD_REGISTER_NUMBER;
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if (size == 4)
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data = val;
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else {
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if (msc_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
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where, &data))
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return -1;
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if (size == 1)
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data = (data & ~(0xff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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else if (size == 2)
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data = (data & ~(0xffff << ((where & 3) << 3))) |
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(val << ((where & 3) << 3));
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}
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if (msc_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn, where,
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&data))
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return -1;
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return PCIBIOS_SUCCESSFUL;
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}
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struct pci_ops msc_pci_ops = {
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.read = msc_pcibios_read,
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.write = msc_pcibios_write
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};
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