1509e93916
commit 950b879b7f0251317d26bae0687e72592d607532 upstream.
In commit 588a513d3425 ("arm64: Fix race condition on PG_dcache_clean
in __sync_icache_dcache()"), we found RISC-V has the same issue as the
previous arm64. The previous implementation didn't guarantee the correct
sequence of operations, which means flush_icache_all() hasn't been
called when the PG_dcache_clean was set. That would cause a risk of page
synchronization.
Fixes:
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.. | ||
cacheflush.c | ||
context.c | ||
extable.c | ||
fault.c | ||
hugetlbpage.c | ||
init.c | ||
ioremap.c | ||
Makefile | ||
sifive_l2_cache.c | ||
tlbflush.c |