2d4e6ce22c
[ Upstream commit 28b2f82e0383e27476be8a5e13d2aea07ebeb275 ] Fix below division by zero warning: [ 3.176443] Division by zero in kernel. [ 3.181809] CPU: 0 PID: 88 Comm: kworker/0:2 Not tainted 5.3.0-rc2-next-20190730-63758-ge08da51-dirty #124 [ 3.191817] Hardware name: Freescale i.MX7ULP (Device Tree) [ 3.197821] Workqueue: events dbs_work_handler [ 3.202849] [<c01127d8>] (unwind_backtrace) from [<c010cd80>] (show_stack+0x10/0x14) [ 3.211058] [<c010cd80>] (show_stack) from [<c0c77e68>] (dump_stack+0xd8/0x110) [ 3.218820] [<c0c77e68>] (dump_stack) from [<c0c753c0>] (Ldiv0_64+0x8/0x18) [ 3.226263] [<c0c753c0>] (Ldiv0_64) from [<c05984b4>] (clk_pfdv2_set_rate+0x54/0xac) [ 3.234487] [<c05984b4>] (clk_pfdv2_set_rate) from [<c059192c>] (clk_change_rate+0x1a4/0x698) [ 3.243468] [<c059192c>] (clk_change_rate) from [<c0591a08>] (clk_change_rate+0x280/0x698) [ 3.252180] [<c0591a08>] (clk_change_rate) from [<c0591fc0>] (clk_core_set_rate_nolock+0x1a0/0x278) [ 3.261679] [<c0591fc0>] (clk_core_set_rate_nolock) from [<c05920c8>] (clk_set_rate+0x30/0x64) [ 3.270743] [<c05920c8>] (clk_set_rate) from [<c089cb88>] (imx7ulp_set_target+0x184/0x2a4) [ 3.279501] [<c089cb88>] (imx7ulp_set_target) from [<c0896358>] (__cpufreq_driver_target+0x188/0x514) [ 3.289196] [<c0896358>] (__cpufreq_driver_target) from [<c0899b0c>] (od_dbs_update+0x130/0x15c) [ 3.298438] [<c0899b0c>] (od_dbs_update) from [<c089a5d0>] (dbs_work_handler+0x2c/0x5c) [ 3.306914] [<c089a5d0>] (dbs_work_handler) from [<c0156858>] (process_one_work+0x2ac/0x704) [ 3.315826] [<c0156858>] (process_one_work) from [<c0156cdc>] (worker_thread+0x2c/0x574) [ 3.324404] [<c0156cdc>] (worker_thread) from [<c015cfe8>] (kthread+0x134/0x148) [ 3.332278] [<c015cfe8>] (kthread) from [<c01010b4>] (ret_from_fork+0x14/0x20) [ 3.339858] Exception stack(0xe82d5fb0 to 0xe82d5ff8) [ 3.345314] 5fa0: 00000000 00000000 00000000 00000000 [ 3.353926] 5fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 [ 3.362519] 5fe0: 00000000 00000000 00000000 00000000 00000013 00000000 Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
211 lines
4.1 KiB
C
211 lines
4.1 KiB
C
// SPDX-License-Identifier: GPL-2.0+
|
|
/*
|
|
* Copyright (C) 2016 Freescale Semiconductor, Inc.
|
|
* Copyright 2017~2018 NXP
|
|
*
|
|
* Author: Dong Aisheng <aisheng.dong@nxp.com>
|
|
*
|
|
*/
|
|
|
|
#include <linux/clk-provider.h>
|
|
#include <linux/err.h>
|
|
#include <linux/io.h>
|
|
#include <linux/iopoll.h>
|
|
#include <linux/slab.h>
|
|
|
|
#include "clk.h"
|
|
|
|
/**
|
|
* struct clk_pfdv2 - IMX PFD clock
|
|
* @clk_hw: clock source
|
|
* @reg: PFD register address
|
|
* @gate_bit: Gate bit offset
|
|
* @vld_bit: Valid bit offset
|
|
* @frac_off: PLL Fractional Divider offset
|
|
*/
|
|
|
|
struct clk_pfdv2 {
|
|
struct clk_hw hw;
|
|
void __iomem *reg;
|
|
u8 gate_bit;
|
|
u8 vld_bit;
|
|
u8 frac_off;
|
|
};
|
|
|
|
#define to_clk_pfdv2(_hw) container_of(_hw, struct clk_pfdv2, hw)
|
|
|
|
#define CLK_PFDV2_FRAC_MASK 0x3f
|
|
|
|
#define LOCK_TIMEOUT_US USEC_PER_MSEC
|
|
|
|
static DEFINE_SPINLOCK(pfd_lock);
|
|
|
|
static int clk_pfdv2_wait(struct clk_pfdv2 *pfd)
|
|
{
|
|
u32 val;
|
|
|
|
return readl_poll_timeout(pfd->reg, val, val & (1 << pfd->vld_bit),
|
|
0, LOCK_TIMEOUT_US);
|
|
}
|
|
|
|
static int clk_pfdv2_enable(struct clk_hw *hw)
|
|
{
|
|
struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
|
|
unsigned long flags;
|
|
u32 val;
|
|
|
|
spin_lock_irqsave(&pfd_lock, flags);
|
|
val = readl_relaxed(pfd->reg);
|
|
val &= ~(1 << pfd->gate_bit);
|
|
writel_relaxed(val, pfd->reg);
|
|
spin_unlock_irqrestore(&pfd_lock, flags);
|
|
|
|
return clk_pfdv2_wait(pfd);
|
|
}
|
|
|
|
static void clk_pfdv2_disable(struct clk_hw *hw)
|
|
{
|
|
struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
|
|
unsigned long flags;
|
|
u32 val;
|
|
|
|
spin_lock_irqsave(&pfd_lock, flags);
|
|
val = readl_relaxed(pfd->reg);
|
|
val |= (1 << pfd->gate_bit);
|
|
writel_relaxed(val, pfd->reg);
|
|
spin_unlock_irqrestore(&pfd_lock, flags);
|
|
}
|
|
|
|
static unsigned long clk_pfdv2_recalc_rate(struct clk_hw *hw,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
|
|
u64 tmp = parent_rate;
|
|
u8 frac;
|
|
|
|
frac = (readl_relaxed(pfd->reg) >> pfd->frac_off)
|
|
& CLK_PFDV2_FRAC_MASK;
|
|
|
|
if (!frac) {
|
|
pr_debug("clk_pfdv2: %s invalid pfd frac value 0\n",
|
|
clk_hw_get_name(hw));
|
|
return 0;
|
|
}
|
|
|
|
tmp *= 18;
|
|
do_div(tmp, frac);
|
|
|
|
return tmp;
|
|
}
|
|
|
|
static long clk_pfdv2_round_rate(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long *prate)
|
|
{
|
|
u64 tmp = *prate;
|
|
u8 frac;
|
|
|
|
tmp = tmp * 18 + rate / 2;
|
|
do_div(tmp, rate);
|
|
frac = tmp;
|
|
|
|
if (frac < 12)
|
|
frac = 12;
|
|
else if (frac > 35)
|
|
frac = 35;
|
|
|
|
tmp = *prate;
|
|
tmp *= 18;
|
|
do_div(tmp, frac);
|
|
|
|
return tmp;
|
|
}
|
|
|
|
static int clk_pfdv2_is_enabled(struct clk_hw *hw)
|
|
{
|
|
struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
|
|
|
|
if (readl_relaxed(pfd->reg) & (1 << pfd->gate_bit))
|
|
return 0;
|
|
|
|
return 1;
|
|
}
|
|
|
|
static int clk_pfdv2_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
unsigned long parent_rate)
|
|
{
|
|
struct clk_pfdv2 *pfd = to_clk_pfdv2(hw);
|
|
unsigned long flags;
|
|
u64 tmp = parent_rate;
|
|
u32 val;
|
|
u8 frac;
|
|
|
|
if (!rate)
|
|
return -EINVAL;
|
|
|
|
/* PFD can NOT change rate without gating */
|
|
WARN_ON(clk_pfdv2_is_enabled(hw));
|
|
|
|
tmp = tmp * 18 + rate / 2;
|
|
do_div(tmp, rate);
|
|
frac = tmp;
|
|
if (frac < 12)
|
|
frac = 12;
|
|
else if (frac > 35)
|
|
frac = 35;
|
|
|
|
spin_lock_irqsave(&pfd_lock, flags);
|
|
val = readl_relaxed(pfd->reg);
|
|
val &= ~(CLK_PFDV2_FRAC_MASK << pfd->frac_off);
|
|
val |= frac << pfd->frac_off;
|
|
writel_relaxed(val, pfd->reg);
|
|
spin_unlock_irqrestore(&pfd_lock, flags);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct clk_ops clk_pfdv2_ops = {
|
|
.enable = clk_pfdv2_enable,
|
|
.disable = clk_pfdv2_disable,
|
|
.recalc_rate = clk_pfdv2_recalc_rate,
|
|
.round_rate = clk_pfdv2_round_rate,
|
|
.set_rate = clk_pfdv2_set_rate,
|
|
.is_enabled = clk_pfdv2_is_enabled,
|
|
};
|
|
|
|
struct clk_hw *imx_clk_pfdv2(const char *name, const char *parent_name,
|
|
void __iomem *reg, u8 idx)
|
|
{
|
|
struct clk_init_data init;
|
|
struct clk_pfdv2 *pfd;
|
|
struct clk_hw *hw;
|
|
int ret;
|
|
|
|
WARN_ON(idx > 3);
|
|
|
|
pfd = kzalloc(sizeof(*pfd), GFP_KERNEL);
|
|
if (!pfd)
|
|
return ERR_PTR(-ENOMEM);
|
|
|
|
pfd->reg = reg;
|
|
pfd->gate_bit = (idx + 1) * 8 - 1;
|
|
pfd->vld_bit = pfd->gate_bit - 1;
|
|
pfd->frac_off = idx * 8;
|
|
|
|
init.name = name;
|
|
init.ops = &clk_pfdv2_ops;
|
|
init.parent_names = &parent_name;
|
|
init.num_parents = 1;
|
|
init.flags = CLK_SET_RATE_GATE;
|
|
|
|
pfd->hw.init = &init;
|
|
|
|
hw = &pfd->hw;
|
|
ret = clk_hw_register(NULL, hw);
|
|
if (ret) {
|
|
kfree(pfd);
|
|
hw = ERR_PTR(ret);
|
|
}
|
|
|
|
return hw;
|
|
}
|