6949a466ba
Add support for WARN_CLK to dump the clock registers and calltrace in case of failure in the kernel message. Change-Id: If7452aaa02cc50deafd6f3721921f66cad9ab932 Signed-off-by: Taniya Das <tdas@codeaurora.org>
111 lines
3.3 KiB
C
111 lines
3.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/* Copyright (c) 2016, 2019-2020, The Linux Foundation. All rights reserved. */
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#ifndef __QCOM_CLK_DEBUG_H__
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#define __QCOM_CLK_DEBUG_H__
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#include <linux/platform_device.h>
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#include "../clk.h"
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/**
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* struct mux_regmap_names - Structure of mux regmap mapping
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* @mux: pointer to a clock debug mux
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* @regmap_name: corresponding regmap name used to match a debug mux to
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its regmap
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*/
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struct mux_regmap_names {
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struct clk_debug_mux *mux;
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const char *regmap_name;
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};
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/* Debugfs Measure Clocks */
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/**
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* struct measure_clk_data - Structure of clk measure
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*
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* @cxo: XO clock.
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* @xo_div4_cbcr: offset of debug XO/4 div register.
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* @ctl_reg: offset of debug control register.
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* @status_reg: offset of debug status register.
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* @cbcr_offset: branch register to turn on debug mux.
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*/
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struct measure_clk_data {
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struct clk *cxo;
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u32 ctl_reg;
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u32 status_reg;
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u32 xo_div4_cbcr;
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};
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/**
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* struct clk_debug_mux - Structure of clock debug mux
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*
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* @mux_sels: indicates the debug mux index at recursive debug mux.
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* @pre_div_val: optional divider values for clocks that were pre-divided
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before feeding into the debug muxes
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* @num_parents: number of parents
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* @regmap: regmaps of debug mux
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* @priv: private measure_clk_data to be used by debug mux
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* @en_mask: indicates the enable bit mask at global clock
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* controller debug mux.
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* @debug_offset: debug mux offset.
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* @post_div_offset: register with post-divider settings for the debug mux.
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* @cbcr_offset: branch register to turn on debug mux.
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* @src_sel_mask: indicates the mask to be used for src selection in
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primary mux.
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* @src_sel_shift: indicates the shift required for source selection in
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primary mux.
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* @post_div_mask: indicates the post div mask to be used for the primary
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mux.
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* @post_div_shift: indicates the shift required for post divider
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selection in primary mux.
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* @period_offset: offset of the period register used to read to determine
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the mc clock period
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* @hw: handle between common and hardware-specific interfaces.
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*/
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struct clk_debug_mux {
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int *mux_sels;
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int *pre_div_vals;
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int num_parents;
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struct regmap *regmap;
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void *priv;
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u32 en_mask;
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u32 debug_offset;
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u32 cbcr_offset;
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u32 src_sel_mask;
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u32 src_sel_shift;
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u32 post_div_offset;
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u32 post_div_mask;
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u32 post_div_shift;
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u32 post_div_val;
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u32 period_offset;
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struct clk_hw hw;
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};
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#define to_clk_measure(_hw) container_of((_hw), struct clk_debug_mux, hw)
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extern const struct clk_ops clk_debug_mux_ops;
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int clk_debug_measure_register(struct clk_hw *hw);
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void clk_debug_measure_add(struct clk_hw *hw, struct dentry *dentry);
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int map_debug_bases(struct platform_device *pdev, const char *base,
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struct clk_debug_mux *mux);
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void clk_common_debug_init(struct clk_hw *hw, struct dentry *dentry);
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extern void clk_debug_print_hw(struct clk_hw *hw, struct seq_file *f);
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#define WARN_CLK(hw, cond, fmt, ...) do { \
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clk_debug_print_hw(hw, NULL); \
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WARN(cond, "%s: " fmt, clk_hw_get_name(hw), ##__VA_ARGS__); \
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} while (0)
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#define clock_debug_output(m, fmt, ...) \
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do { \
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if (m) \
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seq_printf(m, fmt, ##__VA_ARGS__); \
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else \
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pr_info(fmt, ##__VA_ARGS__); \
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} while (0)
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#endif
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