a1472e73e3
The AMD new hardware uses BAR23 and BAR45 as memory windows as compared to previos where BAR1, BAR23 and BAR45 is used for memory windows. This patch add support for both AMD hardwares. Signed-off-by: Sanjay R Mehta <sanju.mehta@amd.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
222 lines
5.9 KiB
C
222 lines
5.9 KiB
C
/*
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* This file is provided under a dual BSD/GPLv2 license. When using or
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* redistributing this file, you may do so under either license.
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*
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* GPL LICENSE SUMMARY
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*
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* Copyright (C) 2016 Advanced Micro Devices, Inc. All Rights Reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of version 2 of the GNU General Public License as
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* published by the Free Software Foundation.
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*
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* BSD LICENSE
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*
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* Copyright (C) 2016 Advanced Micro Devices, Inc. All Rights Reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copy
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* * Neither the name of AMD Corporation nor the names of its
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* contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* AMD PCIe NTB Linux driver
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*
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* Contact Information:
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* Xiangliang Yu <Xiangliang.Yu@amd.com>
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*/
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#ifndef NTB_HW_AMD_H
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#define NTB_HW_AMD_H
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#include <linux/ntb.h>
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#include <linux/pci.h>
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#define AMD_LINK_HB_TIMEOUT msecs_to_jiffies(1000)
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#define AMD_LINK_STATUS_OFFSET 0x68
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#define NTB_LIN_STA_ACTIVE_BIT 0x00000002
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#define NTB_LNK_STA_SPEED_MASK 0x000F0000
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#define NTB_LNK_STA_WIDTH_MASK 0x03F00000
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#define NTB_LNK_STA_ACTIVE(x) (!!((x) & NTB_LIN_STA_ACTIVE_BIT))
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#define NTB_LNK_STA_SPEED(x) (((x) & NTB_LNK_STA_SPEED_MASK) >> 16)
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#define NTB_LNK_STA_WIDTH(x) (((x) & NTB_LNK_STA_WIDTH_MASK) >> 20)
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#ifndef read64
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#ifdef readq
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#define read64 readq
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#else
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#define read64 _read64
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static inline u64 _read64(void __iomem *mmio)
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{
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u64 low, high;
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low = readl(mmio);
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high = readl(mmio + sizeof(u32));
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return low | (high << 32);
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}
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#endif
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#endif
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#ifndef write64
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#ifdef writeq
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#define write64 writeq
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#else
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#define write64 _write64
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static inline void _write64(u64 val, void __iomem *mmio)
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{
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writel(val, mmio);
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writel(val >> 32, mmio + sizeof(u32));
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}
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#endif
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#endif
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enum {
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/* AMD NTB Capability */
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AMD_DB_CNT = 16,
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AMD_MSIX_VECTOR_CNT = 24,
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AMD_SPADS_CNT = 16,
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/* AMD NTB register offset */
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AMD_CNTL_OFFSET = 0x200,
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/* NTB control register bits */
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PMM_REG_CTL = BIT(21),
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SMM_REG_CTL = BIT(20),
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SMM_REG_ACC_PATH = BIT(18),
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PMM_REG_ACC_PATH = BIT(17),
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NTB_CLK_EN = BIT(16),
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AMD_STA_OFFSET = 0x204,
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AMD_PGSLV_OFFSET = 0x208,
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AMD_SPAD_MUX_OFFSET = 0x20C,
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AMD_SPAD_OFFSET = 0x210,
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AMD_RSMU_HCID = 0x250,
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AMD_RSMU_SIID = 0x254,
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AMD_PSION_OFFSET = 0x300,
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AMD_SSION_OFFSET = 0x330,
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AMD_MMINDEX_OFFSET = 0x400,
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AMD_MMDATA_OFFSET = 0x404,
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AMD_SIDEINFO_OFFSET = 0x408,
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AMD_SIDE_MASK = BIT(0),
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AMD_SIDE_READY = BIT(1),
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/* limit register */
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AMD_ROMBARLMT_OFFSET = 0x410,
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AMD_BAR1LMT_OFFSET = 0x414,
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AMD_BAR23LMT_OFFSET = 0x418,
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AMD_BAR45LMT_OFFSET = 0x420,
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/* xlat address */
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AMD_POMBARXLAT_OFFSET = 0x428,
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AMD_BAR1XLAT_OFFSET = 0x430,
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AMD_BAR23XLAT_OFFSET = 0x438,
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AMD_BAR45XLAT_OFFSET = 0x440,
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/* doorbell and interrupt */
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AMD_DBFM_OFFSET = 0x450,
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AMD_DBREQ_OFFSET = 0x454,
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AMD_MIRRDBSTAT_OFFSET = 0x458,
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AMD_DBMASK_OFFSET = 0x45C,
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AMD_DBSTAT_OFFSET = 0x460,
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AMD_INTMASK_OFFSET = 0x470,
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AMD_INTSTAT_OFFSET = 0x474,
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/* event type */
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AMD_PEER_FLUSH_EVENT = BIT(0),
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AMD_PEER_RESET_EVENT = BIT(1),
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AMD_PEER_D3_EVENT = BIT(2),
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AMD_PEER_PMETO_EVENT = BIT(3),
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AMD_PEER_D0_EVENT = BIT(4),
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AMD_LINK_UP_EVENT = BIT(5),
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AMD_LINK_DOWN_EVENT = BIT(6),
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AMD_EVENT_INTMASK = (AMD_PEER_FLUSH_EVENT |
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AMD_PEER_RESET_EVENT | AMD_PEER_D3_EVENT |
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AMD_PEER_PMETO_EVENT | AMD_PEER_D0_EVENT |
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AMD_LINK_UP_EVENT | AMD_LINK_DOWN_EVENT),
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AMD_PMESTAT_OFFSET = 0x480,
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AMD_PMSGTRIG_OFFSET = 0x490,
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AMD_LTRLATENCY_OFFSET = 0x494,
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AMD_FLUSHTRIG_OFFSET = 0x498,
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/* SMU register*/
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AMD_SMUACK_OFFSET = 0x4A0,
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AMD_SINRST_OFFSET = 0x4A4,
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AMD_RSPNUM_OFFSET = 0x4A8,
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AMD_SMU_SPADMUTEX = 0x4B0,
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AMD_SMU_SPADOFFSET = 0x4B4,
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AMD_PEER_OFFSET = 0x400,
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};
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struct ntb_dev_data {
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const unsigned char mw_count;
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const unsigned int mw_idx;
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};
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struct amd_ntb_dev;
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struct amd_ntb_vec {
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struct amd_ntb_dev *ndev;
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int num;
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};
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struct amd_ntb_dev {
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struct ntb_dev ntb;
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u32 ntb_side;
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u32 lnk_sta;
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u32 cntl_sta;
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u32 peer_sta;
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struct ntb_dev_data *dev_data;
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unsigned char mw_count;
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unsigned char spad_count;
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unsigned char db_count;
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unsigned char msix_vec_count;
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u64 db_valid_mask;
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u64 db_mask;
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u32 int_mask;
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struct msix_entry *msix;
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struct amd_ntb_vec *vec;
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/* synchronize rmw access of db_mask and hw reg */
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spinlock_t db_mask_lock;
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void __iomem *self_mmio;
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void __iomem *peer_mmio;
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unsigned int self_spad;
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unsigned int peer_spad;
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struct delayed_work hb_timer;
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struct dentry *debugfs_dir;
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struct dentry *debugfs_info;
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};
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#define ntb_ndev(__ntb) container_of(__ntb, struct amd_ntb_dev, ntb)
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#define hb_ndev(__work) container_of(__work, struct amd_ntb_dev, hb_timer.work)
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#endif
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