23b65c3a24
git-subtree-dir: techpack/display git-subtree-mainline:2d46776923
git-subtree-split:64f31403b4
Change-Id: I7f4c42a3ba6b11a8db861cdd171a52d8f58f2e06
723 lines
17 KiB
C
723 lines
17 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2015-2020, The Linux Foundation. All rights reserved.
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*/
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#ifndef _SDE_HW_MDSS_H
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#define _SDE_HW_MDSS_H
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#include <linux/kernel.h>
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#include <linux/err.h>
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#include "msm_drv.h"
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#define SDE_DBG_NAME "sde"
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#define SDE_NONE 0
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#ifndef SDE_CSC_MATRIX_COEFF_SIZE
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#define SDE_CSC_MATRIX_COEFF_SIZE 9
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#endif
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#ifndef SDE_CSC_CLAMP_SIZE
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#define SDE_CSC_CLAMP_SIZE 6
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#endif
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#ifndef SDE_CSC_BIAS_SIZE
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#define SDE_CSC_BIAS_SIZE 3
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#endif
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#ifndef SDE_MAX_PLANES
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#define SDE_MAX_PLANES 4
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#endif
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#define PIPES_PER_STAGE 2
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#ifndef SDE_MAX_DE_CURVES
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#define SDE_MAX_DE_CURVES 3
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#endif
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#define MAX_DSI_DISPLAYS 2
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#define MAX_DATA_PATH_PER_DSIPLAY 4
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enum sde_format_flags {
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SDE_FORMAT_FLAG_YUV_BIT,
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SDE_FORMAT_FLAG_DX_BIT,
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SDE_FORMAT_FLAG_COMPRESSED_BIT,
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SDE_FORMAT_FLAG_BIT_MAX,
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};
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#define SDE_FORMAT_FLAG_YUV BIT(SDE_FORMAT_FLAG_YUV_BIT)
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#define SDE_FORMAT_FLAG_DX BIT(SDE_FORMAT_FLAG_DX_BIT)
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#define SDE_FORMAT_FLAG_COMPRESSED BIT(SDE_FORMAT_FLAG_COMPRESSED_BIT)
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#define SDE_FORMAT_IS_YUV(X) \
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(test_bit(SDE_FORMAT_FLAG_YUV_BIT, (X)->flag))
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#define SDE_FORMAT_IS_DX(X) \
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(test_bit(SDE_FORMAT_FLAG_DX_BIT, (X)->flag))
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#define SDE_FORMAT_IS_LINEAR(X) ((X)->fetch_mode == SDE_FETCH_LINEAR)
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#define SDE_FORMAT_IS_TILE(X) \
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(((X)->fetch_mode == SDE_FETCH_UBWC) && \
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!test_bit(SDE_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag))
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#define SDE_FORMAT_IS_UBWC(X) \
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(((X)->fetch_mode == SDE_FETCH_UBWC) && \
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test_bit(SDE_FORMAT_FLAG_COMPRESSED_BIT, (X)->flag))
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#define SDE_BLEND_FG_ALPHA_FG_CONST (0 << 0)
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#define SDE_BLEND_FG_ALPHA_BG_CONST (1 << 0)
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#define SDE_BLEND_FG_ALPHA_FG_PIXEL (2 << 0)
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#define SDE_BLEND_FG_ALPHA_BG_PIXEL (3 << 0)
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#define SDE_BLEND_FG_INV_ALPHA (1 << 2)
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#define SDE_BLEND_FG_MOD_ALPHA (1 << 3)
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#define SDE_BLEND_FG_INV_MOD_ALPHA (1 << 4)
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#define SDE_BLEND_FG_TRANSP_EN (1 << 5)
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#define SDE_BLEND_BG_ALPHA_FG_CONST (0 << 8)
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#define SDE_BLEND_BG_ALPHA_BG_CONST (1 << 8)
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#define SDE_BLEND_BG_ALPHA_FG_PIXEL (2 << 8)
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#define SDE_BLEND_BG_ALPHA_BG_PIXEL (3 << 8)
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#define SDE_BLEND_BG_INV_ALPHA (1 << 10)
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#define SDE_BLEND_BG_MOD_ALPHA (1 << 11)
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#define SDE_BLEND_BG_INV_MOD_ALPHA (1 << 12)
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#define SDE_BLEND_BG_TRANSP_EN (1 << 13)
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#define SDE_VSYNC0_SOURCE_GPIO 0
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#define SDE_VSYNC1_SOURCE_GPIO 1
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#define SDE_VSYNC2_SOURCE_GPIO 2
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#define SDE_VSYNC_SOURCE_INTF_0 3
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#define SDE_VSYNC_SOURCE_INTF_1 4
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#define SDE_VSYNC_SOURCE_INTF_2 5
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#define SDE_VSYNC_SOURCE_INTF_3 6
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#define SDE_VSYNC_SOURCE_WD_TIMER_4 11
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#define SDE_VSYNC_SOURCE_WD_TIMER_3 12
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#define SDE_VSYNC_SOURCE_WD_TIMER_2 13
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#define SDE_VSYNC_SOURCE_WD_TIMER_1 14
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#define SDE_VSYNC_SOURCE_WD_TIMER_0 15
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enum sde_hw_blk_type {
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SDE_HW_BLK_TOP = 0,
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SDE_HW_BLK_SSPP,
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SDE_HW_BLK_LM,
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SDE_HW_BLK_DSPP,
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SDE_HW_BLK_DS,
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SDE_HW_BLK_CTL,
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SDE_HW_BLK_CDM,
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SDE_HW_BLK_PINGPONG,
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SDE_HW_BLK_INTF,
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SDE_HW_BLK_WB,
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SDE_HW_BLK_DSC,
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SDE_HW_BLK_VDC,
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SDE_HW_BLK_MERGE_3D,
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SDE_HW_BLK_QDSS,
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SDE_HW_BLK_MAX,
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};
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enum sde_uidle {
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UIDLE = 0x1,
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UIDLE_MAX,
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};
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enum sde_mdp {
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MDP_TOP = 0x1,
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MDP_MAX,
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};
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enum sde_sspp {
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SSPP_NONE,
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SSPP_VIG0,
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SSPP_VIG1,
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SSPP_VIG2,
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SSPP_VIG3,
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SSPP_RGB0,
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SSPP_RGB1,
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SSPP_RGB2,
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SSPP_RGB3,
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SSPP_DMA0,
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SSPP_DMA1,
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SSPP_DMA2,
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SSPP_DMA3,
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SSPP_CURSOR0,
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SSPP_CURSOR1,
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SSPP_MAX
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};
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enum sde_sspp_type {
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SSPP_TYPE_VIG,
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SSPP_TYPE_RGB,
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SSPP_TYPE_DMA,
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SSPP_TYPE_CURSOR,
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SSPP_TYPE_MAX
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};
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enum sde_lm {
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LM_0 = 1,
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LM_1,
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LM_2,
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LM_3,
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LM_4,
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LM_5,
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LM_6,
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LM_MAX
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};
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enum sde_stage {
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SDE_STAGE_BASE = 0,
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SDE_STAGE_0,
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SDE_STAGE_1,
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SDE_STAGE_2,
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SDE_STAGE_3,
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SDE_STAGE_4,
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SDE_STAGE_5,
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SDE_STAGE_6,
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SDE_STAGE_7,
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SDE_STAGE_8,
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SDE_STAGE_9,
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SDE_STAGE_10,
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SDE_STAGE_MAX
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};
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enum sde_dspp {
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DSPP_0 = 1,
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DSPP_1,
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DSPP_2,
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DSPP_3,
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DSPP_MAX
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};
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enum sde_ltm {
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LTM_0 = DSPP_0,
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LTM_1,
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LTM_MAX
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};
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enum sde_rc {
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RC_0 = DSPP_0,
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RC_1,
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RC_MAX
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};
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enum sde_ds {
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DS_TOP,
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DS_0,
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DS_1,
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DS_MAX
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};
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enum sde_ctl {
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CTL_0 = 1,
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CTL_1,
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CTL_2,
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CTL_3,
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CTL_4,
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CTL_5,
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CTL_MAX
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};
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enum sde_cdm {
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CDM_0 = 1,
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CDM_1,
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CDM_MAX
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};
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enum sde_pingpong {
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PINGPONG_0 = 1,
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PINGPONG_1,
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PINGPONG_2,
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PINGPONG_3,
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PINGPONG_4,
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PINGPONG_5,
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PINGPONG_S0,
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PINGPONG_MAX
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};
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enum sde_dsc {
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DSC_NONE = 0,
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DSC_0,
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DSC_1,
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DSC_2,
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DSC_3,
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DSC_4,
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DSC_5,
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DSC_MAX
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};
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enum sde_vdc {
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VDC_NONE = 0,
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VDC_0,
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VDC_1,
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VDC_MAX
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};
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enum sde_intf {
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INTF_0 = 1,
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INTF_1,
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INTF_2,
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INTF_3,
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INTF_4,
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INTF_5,
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INTF_6,
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INTF_MAX
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};
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enum sde_intf_type {
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INTF_NONE = 0x0,
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INTF_DSI = 0x1,
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INTF_HDMI = 0x3,
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INTF_LCDC = 0x5,
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INTF_EDP = 0x9,
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INTF_DP = 0xa,
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INTF_TYPE_MAX,
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/* virtual interfaces */
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INTF_WB = 0x100,
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};
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enum sde_intf_mode {
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INTF_MODE_NONE = 0,
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INTF_MODE_CMD,
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INTF_MODE_VIDEO,
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INTF_MODE_WB_BLOCK,
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INTF_MODE_WB_LINE,
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INTF_MODE_MAX
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};
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enum sde_wb {
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WB_0 = 1,
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WB_1,
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WB_2,
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WB_3,
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WB_MAX
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};
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enum sde_ad {
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AD_0 = 0x1,
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AD_1,
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AD_MAX
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};
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enum sde_cwb {
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CWB_0 = 0x1,
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CWB_1,
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CWB_2,
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CWB_3,
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CWB_4,
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CWB_5,
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CWB_MAX
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};
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enum sde_wd_timer {
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WD_TIMER_0 = 0x1,
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WD_TIMER_1,
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WD_TIMER_2,
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WD_TIMER_3,
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WD_TIMER_4,
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WD_TIMER_5,
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WD_TIMER_MAX
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};
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enum sde_vbif {
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VBIF_0,
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VBIF_1,
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VBIF_MAX,
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VBIF_RT = VBIF_0,
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VBIF_NRT = VBIF_1
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};
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enum sde_iommu_domain {
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SDE_IOMMU_DOMAIN_UNSECURE,
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SDE_IOMMU_DOMAIN_SECURE,
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SDE_IOMMU_DOMAIN_MAX
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};
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enum sde_rot {
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ROT_0 = 1,
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ROT_MAX
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};
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enum sde_merge_3d {
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MERGE_3D_0 = 1,
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MERGE_3D_1,
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MERGE_3D_2,
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MERGE_3D_MAX
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};
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enum sde_qdss {
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QDSS_0,
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QDSS_MAX
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};
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/**
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* SDE HW,Component order color map
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*/
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enum {
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C0_G_Y = 0,
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C1_B_Cb = 1,
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C2_R_Cr = 2,
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C3_ALPHA = 3
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};
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/**
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* enum sde_plane_type - defines how the color component pixel packing
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* @SDE_PLANE_INTERLEAVED : Color components in single plane
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* @SDE_PLANE_PLANAR : Color component in separate planes
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* @SDE_PLANE_PSEUDO_PLANAR : Chroma components interleaved in separate plane
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*/
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enum sde_plane_type {
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SDE_PLANE_INTERLEAVED,
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SDE_PLANE_PLANAR,
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SDE_PLANE_PSEUDO_PLANAR,
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};
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/**
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* enum sde_chroma_samp_type - chroma sub-samplng type
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* @SDE_CHROMA_RGB : No chroma subsampling
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* @SDE_CHROMA_H2V1 : Chroma pixels are horizontally subsampled
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* @SDE_CHROMA_H1V2 : Chroma pixels are vertically subsampled
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* @SDE_CHROMA_420 : 420 subsampling
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*/
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enum sde_chroma_samp_type {
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SDE_CHROMA_RGB,
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SDE_CHROMA_H2V1,
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SDE_CHROMA_H1V2,
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SDE_CHROMA_420
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};
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/**
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* sde_fetch_type - Defines How SDE HW fetches data
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* @SDE_FETCH_LINEAR : fetch is line by line
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* @SDE_FETCH_TILE : fetches data in Z order from a tile
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* @SDE_FETCH_UBWC : fetch and decompress data
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*/
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enum sde_fetch_type {
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SDE_FETCH_LINEAR,
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SDE_FETCH_TILE,
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SDE_FETCH_UBWC
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};
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/**
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* Value of enum chosen to fit the number of bits
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* expected by the HW programming.
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*/
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enum {
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COLOR_ALPHA_1BIT = 0,
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COLOR_ALPHA_4BIT = 1,
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COLOR_4BIT = 0,
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COLOR_5BIT = 1, /* No 5-bit Alpha */
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COLOR_6BIT = 2, /* 6-Bit Alpha also = 2 */
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COLOR_8BIT = 3, /* 8-Bit Alpha also = 3 */
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};
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/**
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* enum sde_3d_blend_mode
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* Desribes how the 3d data is blended
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* @BLEND_3D_NONE : 3d blending not enabled
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* @BLEND_3D_FRAME_INT : Frame interleaving
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* @BLEND_3D_H_ROW_INT : Horizontal row interleaving
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* @BLEND_3D_V_ROW_INT : vertical row interleaving
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* @BLEND_3D_COL_INT : column interleaving
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* @BLEND_3D_MAX :
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*/
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enum sde_3d_blend_mode {
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BLEND_3D_NONE = 0,
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BLEND_3D_FRAME_INT,
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BLEND_3D_H_ROW_INT,
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BLEND_3D_V_ROW_INT,
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BLEND_3D_COL_INT,
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BLEND_3D_MAX
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};
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/** struct sde_format - defines the format configuration which
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* allows SDE HW to correctly fetch and decode the format
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* @base: base msm_format struture containing fourcc code
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* @fetch_planes: how the color components are packed in pixel format
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* @element: element color ordering
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* @bits: element bit widths
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* @chroma_sample: chroma sub-samplng type
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* @unpack_align_msb: unpack aligned, 0 to LSB, 1 to MSB
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* @unpack_tight: 0 for loose, 1 for tight
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* @unpack_count: 0 = 1 component, 1 = 2 component
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* @bpp: bytes per pixel
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* @alpha_enable: whether the format has an alpha channel
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* @num_planes: number of planes (including meta data planes)
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* @fetch_mode: linear, tiled, or ubwc hw fetch behavior
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* @is_yuv: is format a yuv variant
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* @flag: usage bit flags
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* @tile_width: format tile width
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* @tile_height: format tile height
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*/
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struct sde_format {
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struct msm_format base;
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enum sde_plane_type fetch_planes;
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u8 element[SDE_MAX_PLANES];
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u8 bits[SDE_MAX_PLANES];
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enum sde_chroma_samp_type chroma_sample;
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u8 unpack_align_msb;
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u8 unpack_tight;
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u8 unpack_count;
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u8 bpp;
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u8 alpha_enable;
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u8 num_planes;
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enum sde_fetch_type fetch_mode;
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DECLARE_BITMAP(flag, SDE_FORMAT_FLAG_BIT_MAX);
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u16 tile_width;
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u16 tile_height;
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};
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#define to_sde_format(x) container_of(x, struct sde_format, base)
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/**
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* struct sde_hw_fmt_layout - format information of the source pixel data
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* @format: pixel format parameters
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* @num_planes: number of planes (including meta data planes)
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* @width: image width
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* @height: image height
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* @total_size: total size in bytes
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* @plane_addr: address of each plane
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* @plane_size: length of each plane
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* @plane_pitch: pitch of each plane
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*/
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struct sde_hw_fmt_layout {
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const struct sde_format *format;
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uint32_t num_planes;
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uint32_t width;
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uint32_t height;
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uint32_t total_size;
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uint32_t plane_addr[SDE_MAX_PLANES];
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uint32_t plane_size[SDE_MAX_PLANES];
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uint32_t plane_pitch[SDE_MAX_PLANES];
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};
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struct sde_rect {
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u16 x;
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u16 y;
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u16 w;
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u16 h;
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};
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struct sde_csc_cfg {
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/* matrix coefficients in S15.16 format */
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uint32_t csc_mv[SDE_CSC_MATRIX_COEFF_SIZE];
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uint32_t csc_pre_bv[SDE_CSC_BIAS_SIZE];
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uint32_t csc_post_bv[SDE_CSC_BIAS_SIZE];
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uint32_t csc_pre_lv[SDE_CSC_CLAMP_SIZE];
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uint32_t csc_post_lv[SDE_CSC_CLAMP_SIZE];
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};
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/**
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* struct sde_mdss_color - mdss color description
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* color 0 : green
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* color 1 : blue
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* color 2 : red
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* color 3 : alpha
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*/
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struct sde_mdss_color {
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u32 color_0;
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u32 color_1;
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u32 color_2;
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u32 color_3;
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};
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/*
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* Define bit masks for h/w logging.
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*/
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#define SDE_DBG_MASK_NONE (1 << 0)
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#define SDE_DBG_MASK_CDM (1 << 1)
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#define SDE_DBG_MASK_DSPP (1 << 2)
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#define SDE_DBG_MASK_INTF (1 << 3)
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#define SDE_DBG_MASK_LM (1 << 4)
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#define SDE_DBG_MASK_CTL (1 << 5)
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#define SDE_DBG_MASK_PINGPONG (1 << 6)
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#define SDE_DBG_MASK_SSPP (1 << 7)
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#define SDE_DBG_MASK_WB (1 << 8)
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#define SDE_DBG_MASK_TOP (1 << 9)
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#define SDE_DBG_MASK_VBIF (1 << 10)
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#define SDE_DBG_MASK_DSC (1 << 11)
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#define SDE_DBG_MASK_ROT (1 << 12)
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#define SDE_DBG_MASK_DS (1 << 13)
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#define SDE_DBG_MASK_REGDMA (1 << 14)
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#define SDE_DBG_MASK_UIDLE (1 << 15)
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|
#define SDE_DBG_MASK_SID (1 << 15)
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#define SDE_DBG_MASK_QDSS (1 << 16)
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|
#define SDE_DBG_MASK_VDC (1 << 17)
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|
|
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/**
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|
* struct sde_hw_cp_cfg: hardware dspp/lm feature payload.
|
|
* @payload: Feature specific payload.
|
|
* @len: Length of the payload.
|
|
* @ctl: control pointer associated with dspp/lm.
|
|
* @last_feature: last feature that will be set.
|
|
* @num_of_mixers: number of layer mixers for the display.
|
|
* @mixer_info: mixer info pointer associated with lm.
|
|
* @displayv: height of the display.
|
|
* @displayh: width of the display.
|
|
* @dspp[DSPP_MAX]: array of hw_dspp pointers associated with crtc.
|
|
* @broadcast_disabled: flag indicating if broadcast should be avoided when
|
|
* using LUTDMA
|
|
*/
|
|
struct sde_hw_cp_cfg {
|
|
void *payload;
|
|
u32 len;
|
|
void *ctl;
|
|
u32 last_feature;
|
|
u32 num_of_mixers;
|
|
void *mixer_info;
|
|
u32 displayv;
|
|
u32 displayh;
|
|
struct sde_hw_dspp *dspp[DSPP_MAX];
|
|
bool broadcast_disabled;
|
|
};
|
|
|
|
/**
|
|
* struct sde_hw_dim_layer: dim layer configs
|
|
* @flags: Flag to represent INCLUSIVE/EXCLUSIVE
|
|
* @stage: Blending stage of dim layer
|
|
* @color_fill: Color fill to be used for the layer
|
|
* @rect: Dim layer coordinates
|
|
*/
|
|
struct sde_hw_dim_layer {
|
|
uint32_t flags;
|
|
uint32_t stage;
|
|
struct sde_mdss_color color_fill;
|
|
struct sde_rect rect;
|
|
};
|
|
|
|
/**
|
|
* struct sde_splash_mem - Struct contains splah memory info
|
|
* @splash_buf_size: Indicates the size of the memory region
|
|
* @splash_buf_base: Address of specific splash memory region
|
|
* @ramdump_size: Size of ramdump buffer region
|
|
* @ramdump_base: Address of ramdump region reserved by bootloader
|
|
* @ref_cnt: Tracks the map count to help in sharing splash memory
|
|
*/
|
|
struct sde_splash_mem {
|
|
u32 splash_buf_size;
|
|
unsigned long splash_buf_base;
|
|
u32 ramdump_size;
|
|
unsigned long ramdump_base;
|
|
u32 ref_cnt;
|
|
};
|
|
|
|
/**
|
|
* struct sde_sspp_index_info - Struct containing sspp identifier info
|
|
* @sspp: Enum value indicates sspp id
|
|
* @is_virtual: Boolean to identify if virtual or base
|
|
*/
|
|
struct sde_sspp_index_info {
|
|
enum sde_sspp sspp;
|
|
bool is_virtual;
|
|
};
|
|
|
|
/**
|
|
* struct sde_splash_data - Struct contains details of resources and hw blocks
|
|
* used in continuous splash on a specific display.
|
|
* @cont_splash_enabled: Stores the cont_splash status (enabled/disabled)
|
|
* @encoder: Pointer to the drm encoder object used for this display
|
|
* @splash: Pointer to struct sde_splash_mem used for this display
|
|
* @ctl_ids: Stores the valid MDSS ctl block ids for the current mode
|
|
* @lm_ids: Stores the valid MDSS layer mixer block ids for the current mode
|
|
* @dsc_ids: Stores the valid MDSS DSC block ids for the current mode
|
|
* @vdc_ids: Stores the valid MDSS VDC block ids for the current mode
|
|
* @pipes: Array of sspp info detected on this display
|
|
* @ctl_cnt: Stores the active number of MDSS "top" blks of the current mode
|
|
* @lm_cnt: Stores the active number of MDSS "LM" blks for the current mode
|
|
* @dsc_cnt: Stores the active number of MDSS "dsc" blks for the current mode
|
|
* @vdc_cnt: Stores the valid MDSS VDC block ids for the current mode
|
|
* @pipe_cnt: Stores the active number of "sspp" blks connected
|
|
*/
|
|
struct sde_splash_display {
|
|
bool cont_splash_enabled;
|
|
struct drm_encoder *encoder;
|
|
struct sde_splash_mem *splash;
|
|
u8 ctl_ids[MAX_DATA_PATH_PER_DSIPLAY];
|
|
u8 lm_ids[MAX_DATA_PATH_PER_DSIPLAY];
|
|
u8 dsc_ids[MAX_DATA_PATH_PER_DSIPLAY];
|
|
u8 vdc_ids[MAX_DATA_PATH_PER_DSIPLAY];
|
|
struct sde_sspp_index_info pipes[MAX_DATA_PATH_PER_DSIPLAY];
|
|
u8 ctl_cnt;
|
|
u8 lm_cnt;
|
|
u8 dsc_cnt;
|
|
u8 vdc_cnt;
|
|
u8 pipe_cnt;
|
|
};
|
|
|
|
enum sde_handoff_type {
|
|
SDE_SPLASH_HANDOFF,
|
|
SDE_VM_HANDOFF,
|
|
};
|
|
|
|
/**
|
|
* struct sde_splash_data - Struct contains details of continuous splash
|
|
* for all the displays connected by probe time
|
|
* @type: Indicates the type of handoff
|
|
* @num_splash_regions: Indicates number of splash memory regions from dtsi
|
|
* @num_splash_displays: Indicates count of active displays in continuous splash
|
|
* @splash_mem: Array of all struct sde_splash_mem listed from dtsi
|
|
* @splash_display: Array of all struct sde_splash_display
|
|
*/
|
|
struct sde_splash_data {
|
|
enum sde_handoff_type type;
|
|
u32 num_splash_regions;
|
|
u32 num_splash_displays;
|
|
struct sde_splash_mem splash_mem[MAX_DSI_DISPLAYS];
|
|
struct sde_splash_display splash_display[MAX_DSI_DISPLAYS];
|
|
};
|
|
|
|
/**
|
|
* struct sde_hw_tear_check - Struct contains parameters to configure
|
|
* tear-effect module. This structure is used to configure tear-check
|
|
* logic present either in ping-pong or in interface module.
|
|
* @vsync_count: Ratio of MDP VSYNC clk freq(Hz) to refresh rate divided
|
|
* by no of lines
|
|
* @sync_cfg_height: Total vertical lines (display height - 1)
|
|
* @vsync_init_val: Init value to which the read pointer gets loaded at
|
|
* vsync edge
|
|
* @sync_threshold_start: Read pointer threshold start ROI for write operation
|
|
* @sync_threshold_continue: The minimum number of lines the write pointer
|
|
* needs to be above the read pointer
|
|
* @start_pos: The position from which the start_threshold value is added
|
|
* @rd_ptr_irq: The read pointer line at which interrupt has to be generated
|
|
* @wr_ptr_irq: The write pointer line at which interrupt has to be generated
|
|
* @hw_vsync_mode: Sync with external frame sync input
|
|
*/
|
|
struct sde_hw_tear_check {
|
|
u32 vsync_count;
|
|
u32 sync_cfg_height;
|
|
u32 vsync_init_val;
|
|
u32 sync_threshold_start;
|
|
u32 sync_threshold_continue;
|
|
u32 start_pos;
|
|
u32 rd_ptr_irq;
|
|
u32 wr_ptr_irq;
|
|
u8 hw_vsync_mode;
|
|
};
|
|
|
|
/**
|
|
* struct sde_hw_autorefresh - Struct contains parameters to configure
|
|
* auto-refresh mode for command mode panels
|
|
* @enable: Enalbe or disable the auto-refresh mode
|
|
* @frame_count: Auto-refresh frame counter at which update occurs
|
|
*/
|
|
struct sde_hw_autorefresh {
|
|
bool enable;
|
|
u32 frame_count;
|
|
};
|
|
|
|
/**
|
|
* struct sde_hw_pp_vsync_info - Struct contains parameters to configure
|
|
* read and write pointers for command mode panels
|
|
* @pp_idx: Ping-pong block index
|
|
* @intf_idx: Interface block index
|
|
* @rd_ptr_init_val: Value of rd pointer at vsync edge
|
|
* @rd_ptr_frame_count: num frames sent since enabling interface
|
|
* @rd_ptr_line_count: current line on panel (rd ptr)
|
|
* @wr_ptr_line_count: current line within pp fifo (wr ptr)
|
|
* @intf_frame_count: num frames read from intf
|
|
*/
|
|
struct sde_hw_pp_vsync_info {
|
|
u32 pp_idx;
|
|
u32 intf_idx;
|
|
u32 rd_ptr_init_val;
|
|
u32 rd_ptr_frame_count;
|
|
u32 rd_ptr_line_count;
|
|
u32 wr_ptr_line_count;
|
|
u32 intf_frame_count;
|
|
};
|
|
|
|
#endif /* _SDE_HW_MDSS_H */
|