e4409f8201
"LA.UM.9.14.r1-19500-LAHAINA.QSSI12.0" * tag 'LA.UM.9.14.r1-19500-LAHAINA.QSSI12.0' of https://git.codelinaro.org/clo/la/platform/vendor/opensource/display-drivers: disp: msm: use vzalloc for large allocations disp: msm: sde: Fix data width calculation when widebus is enabled drm: msm: call rsc hw_init after hibernation disp: msm: sde: remove redundant backlight update disp: msm: sde: take min ib votes from perf config disp: msm: sde: validate plane mode and gem obj flags disp: msm: dsi: fix compressed RGB101010 support disp: msm: sde: set parent to xo for link clks while enterting suspend disp: msm: sde: while timing engine enabling poll for active region disp: msm: sde: fix null pointer dereference disp: msm: sde: set NOAUTOEN for sde irq to match with power event disp: msm: sde: always set CTL_x_UIDLE_ACTIVE register to "1" disp: msm: sde: move sde power event call into kms post init disp: msm: sde: fix RM poll timeouts during PM suspend/resume usecase disp: msm: sde: remove clearing cur_master in encoder enable function disp: msm: sde: cancel delayed_off_work before reinitialization disp: msm: sde: update TEAR_SYNC_WRCOUNT register before vsync counter disp: msm: sde: disable vsync counter before tear check update disp: msm: sde: disable vsync_in to update tear check disp: msm: sde: avoid tx wait during DMS for targets with dsc rev2 disp: msm: sde: avoid irq enable/disable during modeset disp: msm: fix rsc static wakeup time calculation disp: msm: dsi: allocate DSI command buffer during bind disp: msm: sde: update uidle_db_updates in both enable/disable cases disp: msm: dsi: add API to handle PHY programming during 0p9 collapse disp: msm: sde: modify format specifier disp: msm: dsi: Clear slave dma status only for broadcast command disp: msm: sde: avoid CWB in power on commit disp: msm: sde: avoid sde irq enable or disable when sde irq not active disp: msm: dsi: remove early return from dma_cmd_wait_for_done disp: msm: sde: protect file private structure with mutex lock disp: msm: add support for twm entry disp: msm: sde: add twm mode sysfs mode disp: msm: sde: add sysfs node to give panel power state disp: msm: dsi: Support uncompressed rgb101010 format disp: msm: sde: avoid rsvp_nxt allocation for suspend commit disp: rotator: remove ubwc format support for rotator disp: msm: sde: add changes to allocate compatible cwb mixers in RM disp: msm: sde: add evt log in rsc timer calculation msm: disp: rotator: add ROT macros for logs disp: msm: dp: replace pr_err with DP_ERR disp: msm: dsi: Do not call devm_clk_put() with invalid clk disp: msm: sde: disable CWB crop after cwb session is ended disp: rotator: remove warning log from spin_lock disp: msm: sde: protect file private structure with mutex lock disp: msm: dsi: add support for ultra low power state disp: msm: sde: switch rsc state before CTL_PREPARE in dual display disp: msm: sde: add checks to avoid null pointer dereference drm: msm: dsi: Update DSI parser util to skip disabled child nodes disp: msm: qpic: fix kw issues in QPIC display driver disp: msm: dsi: Fix deadlock issue in debugfs_esd_trigger_check function Change-Id: I4acda3b051e4306f0c1f1a99c9aa61dfeb99ef90
398 lines
9.8 KiB
C
398 lines
9.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Copyright (c) 2015-2021, The Linux Foundation. All rights reserved.
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*/
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#include "sde_hw_mdss.h"
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#include "sde_hwio.h"
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#include "sde_hw_catalog.h"
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#include "sde_hw_wb.h"
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#include "sde_formats.h"
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#include "sde_dbg.h"
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#include "sde_kms.h"
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#define WB_DST_FORMAT 0x000
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#define WB_DST_OP_MODE 0x004
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#define WB_DST_PACK_PATTERN 0x008
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#define WB_DST0_ADDR 0x00C
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#define WB_DST1_ADDR 0x010
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#define WB_DST2_ADDR 0x014
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#define WB_DST3_ADDR 0x018
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#define WB_DST_YSTRIDE0 0x01C
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#define WB_DST_YSTRIDE1 0x020
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#define WB_DST_YSTRIDE1 0x020
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#define WB_DST_DITHER_BITDEPTH 0x024
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#define WB_DST_MATRIX_ROW0 0x030
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#define WB_DST_MATRIX_ROW1 0x034
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#define WB_DST_MATRIX_ROW2 0x038
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#define WB_DST_MATRIX_ROW3 0x03C
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#define WB_DST_WRITE_CONFIG 0x048
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#define WB_ROTATION_DNSCALER 0x050
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#define WB_ROTATOR_PIPE_DOWNSCALER 0x054
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#define WB_N16_INIT_PHASE_X_C03 0x060
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#define WB_N16_INIT_PHASE_X_C12 0x064
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#define WB_N16_INIT_PHASE_Y_C03 0x068
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#define WB_N16_INIT_PHASE_Y_C12 0x06C
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#define WB_OUT_SIZE 0x074
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#define WB_ALPHA_X_VALUE 0x078
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#define WB_DANGER_LUT 0x084
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#define WB_SAFE_LUT 0x088
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#define WB_QOS_CTRL 0x090
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#define WB_CREQ_LUT_0 0x098
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#define WB_CREQ_LUT_1 0x09C
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#define WB_UBWC_STATIC_CTRL 0x144
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#define WB_MUX 0x150
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#define WB_CROP_CTRL 0x154
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#define WB_CROP_OFFSET 0x158
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#define WB_CSC_BASE 0x260
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#define WB_DST_ADDR_SW_STATUS 0x2B0
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#define WB_CDP_CNTL 0x2B4
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#define WB_OUT_IMAGE_SIZE 0x2C0
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#define WB_OUT_XY 0x2C4
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#define CWB_CTRL_SRC_SEL 0x0
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#define CWB_CTRL_MODE 0x4
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/* WB_QOS_CTRL */
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#define WB_QOS_CTRL_DANGER_SAFE_EN BIT(0)
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static struct sde_wb_cfg *_wb_offset(enum sde_wb wb,
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struct sde_mdss_cfg *m,
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void __iomem *addr,
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struct sde_hw_blk_reg_map *b)
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{
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int i;
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for (i = 0; i < m->wb_count; i++) {
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if (wb == m->wb[i].id) {
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b->base_off = addr;
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b->blk_off = m->wb[i].base;
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b->length = m->wb[i].len;
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b->hwversion = m->hwversion;
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b->log_mask = SDE_DBG_MASK_WB;
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return &m->wb[i];
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}
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}
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return ERR_PTR(-EINVAL);
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}
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static void _sde_hw_cwb_ctrl_init(struct sde_mdss_cfg *m,
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void __iomem *addr, struct sde_hw_blk_reg_map *b)
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{
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int i;
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u32 blk_off;
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char name[64] = {0};
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if (!b)
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return;
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b->base_off = addr;
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b->blk_off = m->cwb_blk_off;
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b->length = 0x20;
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b->hwversion = m->hwversion;
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b->log_mask = SDE_DBG_MASK_WB;
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for (i = 0; i < m->pingpong_count; i++) {
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snprintf(name, sizeof(name), "cwb%d", i);
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blk_off = b->blk_off + (m->cwb_blk_stride * i);
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sde_dbg_reg_register_dump_range(SDE_DBG_NAME, name,
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blk_off, blk_off + b->length, 0xff);
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}
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}
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static void sde_hw_wb_setup_outaddress(struct sde_hw_wb *ctx,
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struct sde_hw_wb_cfg *data)
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{
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struct sde_hw_blk_reg_map *c = &ctx->hw;
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SDE_REG_WRITE(c, WB_DST0_ADDR, data->dest.plane_addr[0]);
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SDE_REG_WRITE(c, WB_DST1_ADDR, data->dest.plane_addr[1]);
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SDE_REG_WRITE(c, WB_DST2_ADDR, data->dest.plane_addr[2]);
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SDE_REG_WRITE(c, WB_DST3_ADDR, data->dest.plane_addr[3]);
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}
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static void sde_hw_wb_setup_format(struct sde_hw_wb *ctx,
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struct sde_hw_wb_cfg *data)
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{
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struct sde_hw_blk_reg_map *c = &ctx->hw;
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const struct sde_format *fmt = data->dest.format;
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u32 dst_format, pattern, ystride0, ystride1, outsize, chroma_samp;
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u32 write_config = 0;
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u32 opmode = 0;
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u32 dst_addr_sw = 0;
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chroma_samp = fmt->chroma_sample;
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dst_format = (chroma_samp << 23) |
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(fmt->fetch_planes << 19) |
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(fmt->bits[C3_ALPHA] << 6) |
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(fmt->bits[C2_R_Cr] << 4) |
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(fmt->bits[C1_B_Cb] << 2) |
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(fmt->bits[C0_G_Y] << 0);
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if (fmt->bits[C3_ALPHA] || fmt->alpha_enable) {
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dst_format |= BIT(8); /* DSTC3_EN */
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if (!fmt->alpha_enable ||
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!(ctx->caps->features & BIT(SDE_WB_PIPE_ALPHA)))
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dst_format |= BIT(14); /* DST_ALPHA_X */
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}
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if (SDE_FORMAT_IS_YUV(fmt) &&
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(ctx->caps->features & BIT(SDE_WB_YUV_CONFIG)))
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dst_format |= BIT(15);
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if (SDE_FORMAT_IS_DX(fmt))
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dst_format |= BIT(21);
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pattern = (fmt->element[3] << 24) |
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(fmt->element[2] << 16) |
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(fmt->element[1] << 8) |
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(fmt->element[0] << 0);
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dst_format |= (fmt->unpack_align_msb << 18) |
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(fmt->unpack_tight << 17) |
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((fmt->unpack_count - 1) << 12) |
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((fmt->bpp - 1) << 9);
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ystride0 = data->dest.plane_pitch[0] |
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(data->dest.plane_pitch[1] << 16);
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ystride1 = data->dest.plane_pitch[2] |
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(data->dest.plane_pitch[3] << 16);
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if (data->roi.h && data->roi.w)
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outsize = (data->roi.h << 16) | data->roi.w;
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else
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outsize = (data->dest.height << 16) | data->dest.width;
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if (SDE_FORMAT_IS_UBWC(fmt)) {
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opmode |= BIT(0);
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dst_format |= BIT(31);
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write_config |= (ctx->mdp->highest_bank_bit << 8);
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if (fmt->base.pixel_format == DRM_FORMAT_RGB565)
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write_config |= 0x8;
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if (IS_UBWC_20_SUPPORTED(ctx->catalog->ubwc_version))
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SDE_REG_WRITE(c, WB_UBWC_STATIC_CTRL,
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(ctx->mdp->ubwc_swizzle << 0) |
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(ctx->mdp->highest_bank_bit << 4));
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if (IS_UBWC_10_SUPPORTED(ctx->catalog->ubwc_version))
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SDE_REG_WRITE(c, WB_UBWC_STATIC_CTRL,
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(ctx->mdp->ubwc_swizzle << 0) |
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BIT(8) |
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(ctx->mdp->highest_bank_bit << 4));
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}
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if (data->is_secure)
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dst_addr_sw |= BIT(0);
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SDE_REG_WRITE(c, WB_ALPHA_X_VALUE, 0xFF);
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SDE_REG_WRITE(c, WB_DST_FORMAT, dst_format);
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SDE_REG_WRITE(c, WB_DST_OP_MODE, opmode);
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SDE_REG_WRITE(c, WB_DST_PACK_PATTERN, pattern);
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SDE_REG_WRITE(c, WB_DST_YSTRIDE0, ystride0);
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SDE_REG_WRITE(c, WB_DST_YSTRIDE1, ystride1);
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SDE_REG_WRITE(c, WB_OUT_SIZE, outsize);
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SDE_REG_WRITE(c, WB_DST_WRITE_CONFIG, write_config);
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SDE_REG_WRITE(c, WB_DST_ADDR_SW_STATUS, dst_addr_sw);
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}
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static void sde_hw_wb_roi(struct sde_hw_wb *ctx, struct sde_hw_wb_cfg *wb)
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{
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struct sde_hw_blk_reg_map *c = &ctx->hw;
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u32 image_size, out_size, out_xy;
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image_size = (wb->dest.height << 16) | wb->dest.width;
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out_xy = (wb->roi.y << 16) | wb->roi.x;
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out_size = (wb->roi.h << 16) | wb->roi.w;
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SDE_REG_WRITE(c, WB_OUT_IMAGE_SIZE, image_size);
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SDE_REG_WRITE(c, WB_OUT_XY, out_xy);
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SDE_REG_WRITE(c, WB_OUT_SIZE, out_size);
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}
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static void sde_hw_wb_crop(struct sde_hw_wb *ctx, struct sde_hw_wb_cfg *wb, bool crop)
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{
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struct sde_hw_blk_reg_map *c = &ctx->hw;
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u32 crop_xy;
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if (crop) {
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crop_xy = (wb->crop.y << 16) | wb->crop.x;
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SDE_REG_WRITE(c, WB_CROP_CTRL, 0x1);
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SDE_REG_WRITE(c, WB_CROP_OFFSET, crop_xy);
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} else {
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SDE_REG_WRITE(c, WB_CROP_CTRL, 0x0);
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}
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}
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static void sde_hw_wb_setup_qos_lut(struct sde_hw_wb *ctx,
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struct sde_hw_wb_qos_cfg *cfg)
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{
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struct sde_hw_blk_reg_map *c = &ctx->hw;
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u32 qos_ctrl = 0;
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if (!ctx || !cfg)
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return;
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SDE_REG_WRITE(c, WB_DANGER_LUT, cfg->danger_lut);
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SDE_REG_WRITE(c, WB_SAFE_LUT, cfg->safe_lut);
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if (ctx->caps && test_bit(SDE_WB_QOS_8LVL, &ctx->caps->features)) {
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SDE_REG_WRITE(c, WB_CREQ_LUT_0, cfg->creq_lut);
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SDE_REG_WRITE(c, WB_CREQ_LUT_1, cfg->creq_lut >> 32);
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}
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if (cfg->danger_safe_en)
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qos_ctrl |= WB_QOS_CTRL_DANGER_SAFE_EN;
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SDE_REG_WRITE(c, WB_QOS_CTRL, qos_ctrl);
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}
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static void sde_hw_wb_setup_cdp(struct sde_hw_wb *ctx,
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struct sde_hw_wb_cdp_cfg *cfg)
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{
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struct sde_hw_blk_reg_map *c;
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u32 cdp_cntl = 0;
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if (!ctx || !cfg)
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return;
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c = &ctx->hw;
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if (cfg->enable)
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cdp_cntl |= BIT(0);
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if (cfg->ubwc_meta_enable)
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cdp_cntl |= BIT(1);
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if (cfg->preload_ahead == SDE_WB_CDP_PRELOAD_AHEAD_64)
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cdp_cntl |= BIT(3);
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SDE_REG_WRITE(c, WB_CDP_CNTL, cdp_cntl);
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}
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static void sde_hw_wb_bind_pingpong_blk(
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struct sde_hw_wb *ctx,
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bool enable,
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const enum sde_pingpong pp)
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{
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struct sde_hw_blk_reg_map *c;
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int mux_cfg = 0xF;
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if (!ctx)
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return;
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c = &ctx->hw;
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if (enable)
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mux_cfg = (pp - PINGPONG_0) & 0x7;
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SDE_REG_WRITE(c, WB_MUX, mux_cfg);
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}
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static void sde_hw_wb_program_cwb_ctrl(struct sde_hw_wb *ctx,
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const enum sde_cwb cur_idx, const enum sde_cwb data_src,
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bool dspp_out, bool enable)
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{
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struct sde_hw_blk_reg_map *c;
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u32 blk_base;
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if (!ctx)
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return;
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c = &ctx->cwb_hw;
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blk_base = ctx->catalog->cwb_blk_stride * (cur_idx - CWB_0);
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if (enable) {
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SDE_REG_WRITE(c, blk_base + CWB_CTRL_SRC_SEL, data_src - CWB_0);
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SDE_REG_WRITE(c, blk_base + CWB_CTRL_MODE, dspp_out);
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} else {
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SDE_REG_WRITE(c, blk_base + CWB_CTRL_SRC_SEL, 0xf);
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SDE_REG_WRITE(c, blk_base + CWB_CTRL_MODE, 0x0);
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}
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}
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static void _setup_wb_ops(struct sde_hw_wb_ops *ops,
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unsigned long features)
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{
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ops->setup_outaddress = sde_hw_wb_setup_outaddress;
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ops->setup_outformat = sde_hw_wb_setup_format;
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if (test_bit(SDE_WB_XY_ROI_OFFSET, &features))
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ops->setup_roi = sde_hw_wb_roi;
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if (test_bit(SDE_WB_CROP, &features))
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ops->setup_crop = sde_hw_wb_crop;
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if (test_bit(SDE_WB_QOS, &features))
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ops->setup_qos_lut = sde_hw_wb_setup_qos_lut;
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if (test_bit(SDE_WB_CDP, &features))
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ops->setup_cdp = sde_hw_wb_setup_cdp;
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if (test_bit(SDE_WB_INPUT_CTRL, &features))
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ops->bind_pingpong_blk = sde_hw_wb_bind_pingpong_blk;
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if (test_bit(SDE_WB_CWB_CTRL, &features))
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ops->program_cwb_ctrl = sde_hw_wb_program_cwb_ctrl;
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}
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static struct sde_hw_blk_ops sde_hw_ops = {
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.start = NULL,
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.stop = NULL,
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};
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struct sde_hw_wb *sde_hw_wb_init(enum sde_wb idx,
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void __iomem *addr,
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struct sde_mdss_cfg *m,
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struct sde_hw_mdp *hw_mdp)
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{
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struct sde_hw_wb *c;
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struct sde_wb_cfg *cfg;
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int rc;
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if (!addr || !m || !hw_mdp)
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return ERR_PTR(-EINVAL);
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c = kzalloc(sizeof(*c), GFP_KERNEL);
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if (!c)
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return ERR_PTR(-ENOMEM);
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cfg = _wb_offset(idx, m, addr, &c->hw);
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if (IS_ERR(cfg)) {
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WARN(1, "Unable to find wb idx=%d\n", idx);
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kfree(c);
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return ERR_PTR(-EINVAL);
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}
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/* Assign ops */
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c->catalog = m;
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c->mdp = &m->mdp[0];
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c->idx = idx;
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c->caps = cfg;
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_setup_wb_ops(&c->ops, c->caps->features);
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c->hw_mdp = hw_mdp;
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rc = sde_hw_blk_init(&c->base, SDE_HW_BLK_WB, idx, &sde_hw_ops);
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if (rc) {
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SDE_ERROR("failed to init hw blk %d\n", rc);
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goto blk_init_error;
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}
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sde_dbg_reg_register_dump_range(SDE_DBG_NAME, cfg->name, c->hw.blk_off,
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c->hw.blk_off + c->hw.length, c->hw.xin_id);
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if (test_bit(SDE_WB_CWB_CTRL, &cfg->features))
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_sde_hw_cwb_ctrl_init(m, addr, &c->cwb_hw);
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return c;
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blk_init_error:
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kzfree(c);
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return ERR_PTR(rc);
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}
|
|
|
|
void sde_hw_wb_destroy(struct sde_hw_wb *hw_wb)
|
|
{
|
|
if (hw_wb)
|
|
sde_hw_blk_destroy(&hw_wb->base);
|
|
kfree(hw_wb);
|
|
}
|