c7b91c4798
Add hardware key manager driver in the HLOS kernel to facilitate storage encryption using HWKM. Change-Id: I3531ab083443e2ef41ee5990386b9052ea69841d Signed-off-by: Gaurav Kashyap <gaurkash@codeaurora.org>
262 lines
11 KiB
C
262 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*/
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#ifndef _QTI_HARDWARE_KEY_MANAGER_REGS_H_
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#define _QTI_HARDWARE_KEY_MANAGER_REGS_H_
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#define HWKM_VERSION_STEP_REV_MASK 0xFFFF
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#define HWKM_VERSION_STEP_REV 0 /* bit 15-0 */
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#define HWKM_VERSION_MAJOR_REV_MASK 0xFF000000
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#define HWKM_VERSION_MAJOR_REV 24 /* bit 31-24 */
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#define HWKM_VERSION_MINOR_REV_MASK 0xFF0000
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#define HWKM_VERSION_MINOR_REV 16 /* bit 23-16 */
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/* QTI HWKM master registers from SWI */
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/* QTI HWKM master shared registers */
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#define QTI_HWKM_MASTER_RG_IPCAT_VERSION 0x0000
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#define QTI_HWKM_MASTER_RG_KEY_POLICY_VERSION 0x0004
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#define QTI_HWKM_MASTER_RG_SHARED_STATUS 0x0008
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#define QTI_HWKM_MASTER_RG_KEYTABLE_SIZE 0x000C
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/* QTI HWKM master register bank 2 */
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#define QTI_HWKM_MASTER_RG_BANK2_BANKN_CTL 0x4000
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#define QTI_HWKM_MASTER_RG_BANK2_BANKN_STATUS 0x4004
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#define QTI_HWKM_MASTER_RG_BANK2_BANKN_IRQ_STATUS 0x4008
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#define QTI_HWKM_MASTER_RG_BANK2_BANKN_IRQ_MASK 0x400C
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#define QTI_HWKM_MASTER_RG_BANK2_BANKN_ESR 0x4010
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#define QTI_HWKM_MASTER_RG_BANK2_BANKN_ESR_IRQ_MASK 0x4014
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#define QTI_HWKM_MASTER_RG_BANK2_BANKN_ESYNR 0x4018
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#define QTI_HWKM_MASTER_RG_BANK2_CMD_0 0x401C
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#define QTI_HWKM_MASTER_RG_BANK2_CMD_1 0x4020
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#define QTI_HWKM_MASTER_RG_BANK2_CMD_2 0x4024
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#define QTI_HWKM_MASTER_RG_BANK2_CMD_3 0x4028
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#define QTI_HWKM_MASTER_RG_BANK2_CMD_4 0x402C
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#define QTI_HWKM_MASTER_RG_BANK2_CMD_5 0x4030
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#define QTI_HWKM_MASTER_RG_BANK2_CMD_6 0x4034
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#define QTI_HWKM_MASTER_RG_BANK2_CMD_7 0x4038
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#define QTI_HWKM_MASTER_RG_BANK2_CMD_8 0x403C
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#define QTI_HWKM_MASTER_RG_BANK2_CMD_9 0x4040
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#define QTI_HWKM_MASTER_RG_BANK2_CMD_10 0x4044
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#define QTI_HWKM_MASTER_RG_BANK2_CMD_11 0x4048
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#define QTI_HWKM_MASTER_RG_BANK2_CMD_12 0x404C
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#define QTI_HWKM_MASTER_RG_BANK2_CMD_13 0x4050
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#define QTI_HWKM_MASTER_RG_BANK2_CMD_14 0x4054
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#define QTI_HWKM_MASTER_RG_BANK2_CMD_15 0x4058
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#define QTI_HWKM_MASTER_RG_BANK2_RSP_0 0x405C
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#define QTI_HWKM_MASTER_RG_BANK2_RSP_1 0x4060
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#define QTI_HWKM_MASTER_RG_BANK2_RSP_2 0x4064
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#define QTI_HWKM_MASTER_RG_BANK2_RSP_3 0x4068
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#define QTI_HWKM_MASTER_RG_BANK2_RSP_4 0x406C
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#define QTI_HWKM_MASTER_RG_BANK2_RSP_5 0x4070
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#define QTI_HWKM_MASTER_RG_BANK2_RSP_6 0x4074
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#define QTI_HWKM_MASTER_RG_BANK2_RSP_7 0x4078
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#define QTI_HWKM_MASTER_RG_BANK2_RSP_8 0x407C
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#define QTI_HWKM_MASTER_RG_BANK2_RSP_9 0x4080
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#define QTI_HWKM_MASTER_RG_BANK2_RSP_10 0x4084
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#define QTI_HWKM_MASTER_RG_BANK2_RSP_11 0x4088
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#define QTI_HWKM_MASTER_RG_BANK2_RSP_12 0x408C
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#define QTI_HWKM_MASTER_RG_BANK2_RSP_13 0x4090
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#define QTI_HWKM_MASTER_RG_BANK2_RSP_14 0x4094
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#define QTI_HWKM_MASTER_RG_BANK2_RSP_15 0x4098
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#define QTI_HWKM_MASTER_RG_BANK2_BANKN_IRQ_ROUTING 0x409C
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#define QTI_HWKM_MASTER_RG_BANK2_BANKN_BBAC_0 0x40A0
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#define QTI_HWKM_MASTER_RG_BANK2_BANKN_BBAC_1 0x40A4
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#define QTI_HWKM_MASTER_RG_BANK2_BANKN_BBAC_2 0x40A8
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#define QTI_HWKM_MASTER_RG_BANK2_BANKN_BBAC_3 0x40AC
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#define QTI_HWKM_MASTER_RG_BANK2_BANKN_BBAC_4 0x40B0
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/* QTI HWKM master register bank 3 */
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#define QTI_HWKM_MASTER_RG_BANK3_BANKN_CTL 0x5000
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#define QTI_HWKM_MASTER_RG_BANK3_BANKN_STATUS 0x5004
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#define QTI_HWKM_MASTER_RG_BANK3_BANKN_IRQ_STATUS 0x5008
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#define QTI_HWKM_MASTER_RG_BANK3_BANKN_IRQ_MASK 0x500C
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#define QTI_HWKM_MASTER_RG_BANK3_BANKN_ESR 0x5010
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#define QTI_HWKM_MASTER_RG_BANK3_BANKN_ESR_IRQ_MASK 0x5014
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#define QTI_HWKM_MASTER_RG_BANK3_BANKN_ESYNR 0x5018
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#define QTI_HWKM_MASTER_RG_BANK3_CMD_0 0x501C
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#define QTI_HWKM_MASTER_RG_BANK3_CMD_1 0x5020
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#define QTI_HWKM_MASTER_RG_BANK3_CMD_2 0x5024
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#define QTI_HWKM_MASTER_RG_BANK3_CMD_3 0x5028
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#define QTI_HWKM_MASTER_RG_BANK3_CMD_4 0x502C
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#define QTI_HWKM_MASTER_RG_BANK3_CMD_5 0x5030
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#define QTI_HWKM_MASTER_RG_BANK3_CMD_6 0x5034
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#define QTI_HWKM_MASTER_RG_BANK3_CMD_7 0x5038
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#define QTI_HWKM_MASTER_RG_BANK3_CMD_8 0x503C
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#define QTI_HWKM_MASTER_RG_BANK3_CMD_9 0x5040
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#define QTI_HWKM_MASTER_RG_BANK3_CMD_10 0x5044
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#define QTI_HWKM_MASTER_RG_BANK3_CMD_11 0x5048
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#define QTI_HWKM_MASTER_RG_BANK3_CMD_12 0x504C
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#define QTI_HWKM_MASTER_RG_BANK3_CMD_13 0x5050
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#define QTI_HWKM_MASTER_RG_BANK3_CMD_14 0x5054
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#define QTI_HWKM_MASTER_RG_BANK3_CMD_15 0x5058
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#define QTI_HWKM_MASTER_RG_BANK3_RSP_0 0x505C
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#define QTI_HWKM_MASTER_RG_BANK3_RSP_1 0x5060
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#define QTI_HWKM_MASTER_RG_BANK3_RSP_2 0x5064
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#define QTI_HWKM_MASTER_RG_BANK3_RSP_3 0x5068
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#define QTI_HWKM_MASTER_RG_BANK3_RSP_4 0x506C
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#define QTI_HWKM_MASTER_RG_BANK3_RSP_5 0x5070
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#define QTI_HWKM_MASTER_RG_BANK3_RSP_6 0x5074
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#define QTI_HWKM_MASTER_RG_BANK3_RSP_7 0x5078
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#define QTI_HWKM_MASTER_RG_BANK3_RSP_8 0x507C
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#define QTI_HWKM_MASTER_RG_BANK3_RSP_9 0x5080
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#define QTI_HWKM_MASTER_RG_BANK3_RSP_10 0x5084
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#define QTI_HWKM_MASTER_RG_BANK3_RSP_11 0x5088
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#define QTI_HWKM_MASTER_RG_BANK3_RSP_12 0x508C
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#define QTI_HWKM_MASTER_RG_BANK3_RSP_13 0x5090
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#define QTI_HWKM_MASTER_RG_BANK3_RSP_14 0x5094
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#define QTI_HWKM_MASTER_RG_BANK3_RSP_15 0x5098
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#define QTI_HWKM_MASTER_RG_BANK3_BANKN_IRQ_ROUTING 0x509C
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#define QTI_HWKM_MASTER_RG_BANK3_BANKN_BBAC_0 0x50A0
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#define QTI_HWKM_MASTER_RG_BANK3_BANKN_BBAC_1 0x50A4
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#define QTI_HWKM_MASTER_RG_BANK3_BANKN_BBAC_2 0x50A8
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#define QTI_HWKM_MASTER_RG_BANK3_BANKN_BBAC_3 0x50AC
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#define QTI_HWKM_MASTER_RG_BANK3_BANKN_BBAC_4 0x50B0
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/* QTI HWKM access control registers for Bank 2 */
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#define QTI_HWKM_MASTER_RG_BANK2_AC_BANKN_BBAC_0 0x8000
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#define QTI_HWKM_MASTER_RG_BANK2_AC_BANKN_BBAC_1 0x8004
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#define QTI_HWKM_MASTER_RG_BANK2_AC_BANKN_BBAC_2 0x8008
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#define QTI_HWKM_MASTER_RG_BANK2_AC_BANKN_BBAC_3 0x800C
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#define QTI_HWKM_MASTER_RG_BANK2_AC_BANKN_BBAC_4 0x8010
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/* QTI HWKM access control registers for Bank 3 */
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#define QTI_HWKM_MASTER_RG_BANK3_AC_BANKN_BBAC_0 0x9000
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#define QTI_HWKM_MASTER_RG_BANK3_AC_BANKN_BBAC_1 0x9004
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#define QTI_HWKM_MASTER_RG_BANK3_AC_BANKN_BBAC_2 0x9008
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#define QTI_HWKM_MASTER_RG_BANK3_AC_BANKN_BBAC_3 0x900C
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#define QTI_HWKM_MASTER_RG_BANK3_AC_BANKN_BBAC_4 0x9010
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/* QTI HWKM ICE slave config and status registers */
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#define QTI_HWKM_ICE_RG_TZ_KM_CTL 0x1000
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#define QTI_HWKM_ICE_RG_TZ_KM_STATUS 0x1004
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#define QTI_HWKM_ICE_RG_TZ_KM_STATUS_IRQ_MASK 0x1008
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#define QTI_HWKM_ICE_RG_TZ_KM_BOOT_STAGE_OTP 0x100C
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#define QTI_HWKM_ICE_RG_TZ_KM_DEBUG_CTL 0x1010
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#define QTI_HWKM_ICE_RG_TZ_KM_DEBUG_WRITE 0x1014
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#define QTI_HWKM_ICE_RG_TZ_KM_DEBUG_READ 0x1018
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#define QTI_HWKM_ICE_RG_TZ_TPKEY_RECEIVE_CTL 0x101C
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#define QTI_HWKM_ICE_RG_TZ_TPKEY_RECEIVE_STATUS 0x1020
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#define QTI_HWKM_ICE_RG_TZ_KM_COMMON_IRQ_ROUTING 0x1024
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/* QTI HWKM ICE slave registers from SWI */
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/* QTI HWKM ICE slave shared registers */
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#define QTI_HWKM_ICE_RG_IPCAT_VERSION 0x0000
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#define QTI_HWKM_ICE_RG_KEY_POLICY_VERSION 0x0004
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#define QTI_HWKM_ICE_RG_SHARED_STATUS 0x0008
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#define QTI_HWKM_ICE_RG_KEYTABLE_SIZE 0x000C
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/* QTI HWKM ICE slave register bank 0 */
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#define QTI_HWKM_ICE_RG_BANK0_BANKN_CTL 0x2000
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#define QTI_HWKM_ICE_RG_BANK0_BANKN_STATUS 0x2004
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#define QTI_HWKM_ICE_RG_BANK0_BANKN_IRQ_STATUS 0x2008
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#define QTI_HWKM_ICE_RG_BANK0_BANKN_IRQ_MASK 0x200C
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#define QTI_HWKM_ICE_RG_BANK0_BANKN_ESR 0x2010
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#define QTI_HWKM_ICE_RG_BANK0_BANKN_ESR_IRQ_MASK 0x2014
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#define QTI_HWKM_ICE_RG_BANK0_BANKN_ESYNR 0x2018
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#define QTI_HWKM_ICE_RG_BANK0_CMD_0 0x201C
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#define QTI_HWKM_ICE_RG_BANK0_CMD_1 0x2020
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#define QTI_HWKM_ICE_RG_BANK0_CMD_2 0x2024
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#define QTI_HWKM_ICE_RG_BANK0_CMD_3 0x2028
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#define QTI_HWKM_ICE_RG_BANK0_CMD_4 0x202C
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#define QTI_HWKM_ICE_RG_BANK0_CMD_5 0x2030
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#define QTI_HWKM_ICE_RG_BANK0_CMD_6 0x2034
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#define QTI_HWKM_ICE_RG_BANK0_CMD_7 0x2038
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#define QTI_HWKM_ICE_RG_BANK0_CMD_8 0x203C
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#define QTI_HWKM_ICE_RG_BANK0_CMD_9 0x2040
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#define QTI_HWKM_ICE_RG_BANK0_CMD_10 0x2044
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#define QTI_HWKM_ICE_RG_BANK0_CMD_11 0x2048
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#define QTI_HWKM_ICE_RG_BANK0_CMD_12 0x204C
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#define QTI_HWKM_ICE_RG_BANK0_CMD_13 0x2050
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#define QTI_HWKM_ICE_RG_BANK0_CMD_14 0x2054
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#define QTI_HWKM_ICE_RG_BANK0_CMD_15 0x2058
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#define QTI_HWKM_ICE_RG_BANK0_RSP_0 0x205C
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#define QTI_HWKM_ICE_RG_BANK0_RSP_1 0x2060
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#define QTI_HWKM_ICE_RG_BANK0_RSP_2 0x2064
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#define QTI_HWKM_ICE_RG_BANK0_RSP_3 0x2068
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#define QTI_HWKM_ICE_RG_BANK0_RSP_4 0x206C
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#define QTI_HWKM_ICE_RG_BANK0_RSP_5 0x2070
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#define QTI_HWKM_ICE_RG_BANK0_RSP_6 0x2074
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#define QTI_HWKM_ICE_RG_BANK0_RSP_7 0x2078
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#define QTI_HWKM_ICE_RG_BANK0_RSP_8 0x207C
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#define QTI_HWKM_ICE_RG_BANK0_RSP_9 0x2080
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#define QTI_HWKM_ICE_RG_BANK0_RSP_10 0x2084
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#define QTI_HWKM_ICE_RG_BANK0_RSP_11 0x2088
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#define QTI_HWKM_ICE_RG_BANK0_RSP_12 0x208C
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#define QTI_HWKM_ICE_RG_BANK0_RSP_13 0x2090
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#define QTI_HWKM_ICE_RG_BANK0_RSP_14 0x2094
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#define QTI_HWKM_ICE_RG_BANK0_RSP_15 0x2098
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#define QTI_HWKM_ICE_RG_BANK0_BANKN_IRQ_ROUTING 0x209C
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#define QTI_HWKM_ICE_RG_BANK0_BANKN_BBAC_0 0x20A0
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#define QTI_HWKM_ICE_RG_BANK0_BANKN_BBAC_1 0x20A4
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#define QTI_HWKM_ICE_RG_BANK0_BANKN_BBAC_2 0x20A8
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#define QTI_HWKM_ICE_RG_BANK0_BANKN_BBAC_3 0x20AC
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#define QTI_HWKM_ICE_RG_BANK0_BANKN_BBAC_4 0x20B0
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/* QTI HWKM access control registers for Bank 2 */
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#define QTI_HWKM_ICE_RG_BANK0_AC_BANKN_BBAC_0 0x5000
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#define QTI_HWKM_ICE_RG_BANK0_AC_BANKN_BBAC_1 0x5004
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#define QTI_HWKM_ICE_RG_BANK0_AC_BANKN_BBAC_2 0x5008
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#define QTI_HWKM_ICE_RG_BANK0_AC_BANKN_BBAC_3 0x500C
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#define QTI_HWKM_ICE_RG_BANK0_AC_BANKN_BBAC_4 0x5010
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/* QTI HWKM ICE slave config reg vals */
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/* HWKM_ICEMEM_SLAVE_ICE_KM_RG_TZ_KM_CTL */
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#define CRC_CHECK_EN 0
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#define KEYTABLE_HW_WR_ACCESS_EN 1
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#define KEYTABLE_HW_RD_ACCESS_EN 2
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#define BOOT_INIT0_DISABLE 3
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#define BOOT_INIT1_DISABLE 4
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#define ICE_LEGACY_MODE_EN_OTP 5
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/* HWKM_ICEMEM_SLAVE_ICE_KM_RG_TZ_KM_STATUS */
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#define KT_CLEAR_DONE 0
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#define BOOT_CMD_LIST0_DONE 1
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#define BOOT_CMD_LIST1_DONE 2
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#define KEYTABLE_KEY_POLICY 3
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#define KEYTABLE_INTEGRITY_ERROR 4
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#define KEYTABLE_KEY_SLOT_ERROR 5
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#define KEYTABLE_KEY_SLOT_NOT_EVEN_ERROR 6
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#define KEYTABLE_KEY_SLOT_OUT_OF_RANGE 7
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#define KEYTABLE_KEY_SIZE_ERROR 8
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#define KEYTABLE_OPERATION_ERROR 9
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#define LAST_ACTIVITY_BANK 10
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#define CRYPTO_LIB_BIST_ERROR 13
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#define CRYPTO_LIB_BIST_DONE 14
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#define BIST_ERROR 15
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#define BIST_DONE 16
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#define LAST_ACTIVITY_BANK_MASK 0x1c00
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/* HWKM_ICEMEM_SLAVE_ICE_KM_RG_TZ_TPKEY_RECEIVE_CTL */
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#define TPKEY_EN 8
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/* QTI HWKM Bank status & control reg vals */
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/* HWKM_MASTER_CFG_KM_BANKN_CTL */
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#define CMD_ENABLE_BIT 0
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#define CMD_FIFO_CLEAR_BIT 1
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/* HWKM_MASTER_CFG_KM_BANKN_STATUS */
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#define CURRENT_CMD_REMAINING_LENGTH 0
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#define MOST_RECENT_OPCODE 5
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#define RSP_FIFO_AVAILABLE_DATA 9
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#define CMD_FIFO_AVAILABLE_SPACE 14
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#define ICE_LEGACY_MODE_BIT 19
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#define CMD_FIFO_AVAILABLE_SPACE_MASK 0x7c000
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#define RSP_FIFO_AVAILABLE_DATA_MASK 0x3e00
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#define MOST_RECENT_OPCODE_MASK 0x1e0
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#define CURRENT_CMD_REMAINING_LENGTH_MASK 0x1f
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/* HWKM_MASTER_CFG_KM_BANKN_IRQ_STATUS */
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#define ARB_GRAN_WINNER 0
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#define CMD_DONE_BIT 1
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#define RSP_FIFO_NOT_EMPTY 2
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#define RSP_FIFO_FULL 3
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#define RSP_FIFO_UNDERFLOW 4
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#define CMD_FIFO_UNDERFLOW 5
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#endif /* __QTI_HARDWARE_KEY_MANAGER_REGS_H_ */
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