0178bcb75f
Icnss driver indicates vbatt voltage level to wlan fw based on battery percentage. This change adds power supply framework code to enable icnss2 driver to measure battery percentage and update vbatt volatge level to wlan fw. Change-Id: I376805da38222a5e7a20ae4a1737bc978ee6a9ae Signed-off-by: Sandeep Singh <quic_sandsing@quicinc.com>
513 lines
12 KiB
C
513 lines
12 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2017-2020, 2021, The Linux Foundation.
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* All rights reserved.
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*/
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#ifndef __MAIN_H__
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#define __MAIN_H__
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#include <linux/adc-tm-clients.h>
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#include <linux/iio/consumer.h>
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#include <linux/irqreturn.h>
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#include <linux/kobject.h>
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#include <linux/platform_device.h>
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#include <linux/ipc_logging.h>
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#include <linux/power_supply.h>
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#include <dt-bindings/iio/qcom,spmi-vadc.h>
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#include <soc/qcom/icnss2.h>
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#include <soc/qcom/service-locator.h>
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#include <soc/qcom/service-notifier.h>
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#include "wlan_firmware_service_v01.h"
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#include <linux/timer.h>
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#define WCN6750_DEVICE_ID 0x6750
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#define ADRASTEA_DEVICE_ID 0xabcd
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#define QMI_WLFW_MAX_NUM_MEM_SEG 32
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#define THERMAL_NAME_LENGTH 20
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#define ICNSS_SMEM_VALUE_MASK 0xFFFFFFFF
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#define ICNSS_SMEM_SEQ_NO_POS 16
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#define QCA6750_PATH_PREFIX "qca6750/"
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#define ICNSS_MAX_FILE_NAME 35
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#define ICNSS_PCI_EP_WAKE_OFFSET 4
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#define ICNSS_DISABLE_M3_SSR 0
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#define ICNSS_ENABLE_M3_SSR 1
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extern uint64_t dynamic_feature_mask;
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enum icnss_bdf_type {
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ICNSS_BDF_BIN,
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ICNSS_BDF_ELF,
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ICNSS_BDF_REGDB = 4,
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ICNSS_BDF_DUMMY = 255,
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};
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struct icnss_control_params {
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unsigned long quirks;
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unsigned int qmi_timeout;
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unsigned int bdf_type;
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};
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enum icnss_driver_event_type {
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ICNSS_DRIVER_EVENT_SERVER_ARRIVE,
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ICNSS_DRIVER_EVENT_SERVER_EXIT,
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ICNSS_DRIVER_EVENT_FW_READY_IND,
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ICNSS_DRIVER_EVENT_REGISTER_DRIVER,
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ICNSS_DRIVER_EVENT_UNREGISTER_DRIVER,
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ICNSS_DRIVER_EVENT_PD_SERVICE_DOWN,
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ICNSS_DRIVER_EVENT_FW_EARLY_CRASH_IND,
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ICNSS_DRIVER_EVENT_IDLE_SHUTDOWN,
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ICNSS_DRIVER_EVENT_IDLE_RESTART,
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ICNSS_DRIVER_EVENT_FW_INIT_DONE_IND,
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ICNSS_DRIVER_EVENT_QDSS_TRACE_REQ_MEM,
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ICNSS_DRIVER_EVENT_QDSS_TRACE_SAVE,
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ICNSS_DRIVER_EVENT_QDSS_TRACE_FREE,
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ICNSS_DRIVER_EVENT_M3_DUMP_UPLOAD_REQ,
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ICNSS_DRIVER_EVENT_QDSS_TRACE_REQ_DATA,
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ICNSS_DRIVER_EVENT_SUBSYS_RESTART_LEVEL,
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ICNSS_DRIVER_EVENT_MAX,
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};
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enum icnss_soc_wake_event_type {
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ICNSS_SOC_WAKE_REQUEST_EVENT,
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ICNSS_SOC_WAKE_RELEASE_EVENT,
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ICNSS_SOC_WAKE_EVENT_MAX,
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};
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struct icnss_event_server_arrive_data {
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unsigned int node;
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unsigned int port;
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};
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struct icnss_event_pd_service_down_data {
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bool crashed;
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bool fw_rejuvenate;
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};
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struct icnss_driver_event {
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struct list_head list;
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enum icnss_driver_event_type type;
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bool sync;
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struct completion complete;
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int ret;
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void *data;
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};
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struct icnss_soc_wake_event {
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struct list_head list;
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enum icnss_soc_wake_event_type type;
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bool sync;
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struct completion complete;
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int ret;
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void *data;
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};
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enum icnss_driver_state {
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ICNSS_WLFW_CONNECTED,
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ICNSS_POWER_ON,
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ICNSS_FW_READY,
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ICNSS_DRIVER_PROBED,
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ICNSS_FW_TEST_MODE,
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ICNSS_PM_SUSPEND,
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ICNSS_PM_SUSPEND_NOIRQ,
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ICNSS_SSR_REGISTERED,
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ICNSS_PDR_REGISTERED,
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ICNSS_PD_RESTART,
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ICNSS_WLFW_EXISTS,
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ICNSS_SHUTDOWN_DONE,
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ICNSS_HOST_TRIGGERED_PDR,
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ICNSS_FW_DOWN,
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ICNSS_DRIVER_UNLOADING,
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ICNSS_REJUVENATE,
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ICNSS_MODE_ON,
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ICNSS_BLOCK_SHUTDOWN,
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ICNSS_PDR,
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ICNSS_DEL_SERVER,
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ICNSS_COLD_BOOT_CAL,
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ICNSS_QMI_DMS_CONNECTED,
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};
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struct ce_irq_list {
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int irq;
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irqreturn_t (*handler)(int irq, void *priv);
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};
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struct icnss_vreg_cfg {
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const char *name;
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u32 min_uv;
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u32 max_uv;
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u32 load_ua;
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u32 delay_us;
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u32 need_unvote;
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bool required;
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bool is_supported;
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};
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struct icnss_vreg_info {
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struct list_head list;
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struct regulator *reg;
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struct icnss_vreg_cfg cfg;
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u32 enabled;
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};
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struct icnss_cpr_info {
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resource_size_t tcs_cmd_base_addr;
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resource_size_t tcs_cmd_data_addr;
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void __iomem *tcs_cmd_base_addr_io;
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void __iomem *tcs_cmd_data_addr_io;
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u32 cpr_pmic_addr;
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u32 voltage;
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};
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enum icnss_vreg_type {
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ICNSS_VREG_PRIM,
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};
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struct icnss_clk_cfg {
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const char *name;
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u32 freq;
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u32 required;
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};
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struct icnss_battery_level {
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int lower_battery_threshold;
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int ldo_voltage;
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};
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struct icnss_clk_info {
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struct list_head list;
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struct clk *clk;
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struct icnss_clk_cfg cfg;
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u32 enabled;
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};
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struct icnss_fw_mem {
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size_t size;
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void *va;
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phys_addr_t pa;
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u8 valid;
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u32 type;
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unsigned long attrs;
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};
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enum icnss_smp2p_msg_id {
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ICNSS_POWER_SAVE_ENTER = 1,
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ICNSS_POWER_SAVE_EXIT,
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ICNSS_TRIGGER_SSR,
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ICNSS_PCI_EP_POWER_SAVE_ENTER = 6,
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ICNSS_PCI_EP_POWER_SAVE_EXIT,
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};
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struct icnss_subsys_restart_level_data {
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uint8_t restart_level;
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};
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struct icnss_stats {
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struct {
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uint32_t posted;
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uint32_t processed;
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} events[ICNSS_DRIVER_EVENT_MAX];
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struct {
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u32 posted;
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u32 processed;
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} soc_wake_events[ICNSS_SOC_WAKE_EVENT_MAX];
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struct {
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uint32_t request;
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uint32_t free;
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uint32_t enable;
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uint32_t disable;
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} ce_irqs[ICNSS_MAX_IRQ_REGISTRATIONS];
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struct {
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uint32_t pdr_fw_crash;
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uint32_t pdr_host_error;
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uint32_t root_pd_crash;
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uint32_t root_pd_shutdown;
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} recovery;
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uint32_t pm_suspend;
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uint32_t pm_suspend_err;
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uint32_t pm_resume;
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uint32_t pm_resume_err;
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uint32_t pm_suspend_noirq;
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uint32_t pm_suspend_noirq_err;
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uint32_t pm_resume_noirq;
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uint32_t pm_resume_noirq_err;
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uint32_t pm_stay_awake;
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uint32_t pm_relax;
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uint32_t ind_register_req;
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uint32_t ind_register_resp;
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uint32_t ind_register_err;
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uint32_t msa_info_req;
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uint32_t msa_info_resp;
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uint32_t msa_info_err;
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uint32_t msa_ready_req;
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uint32_t msa_ready_resp;
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uint32_t msa_ready_err;
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uint32_t msa_ready_ind;
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uint32_t cap_req;
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uint32_t cap_resp;
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uint32_t cap_err;
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uint32_t pin_connect_result;
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uint32_t cfg_req;
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uint32_t cfg_resp;
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uint32_t cfg_req_err;
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uint32_t mode_req;
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uint32_t mode_resp;
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uint32_t mode_req_err;
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uint32_t ini_req;
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uint32_t ini_resp;
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uint32_t ini_req_err;
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u32 rejuvenate_ind;
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uint32_t rejuvenate_ack_req;
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uint32_t rejuvenate_ack_resp;
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uint32_t rejuvenate_ack_err;
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uint32_t vbatt_req;
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uint32_t vbatt_resp;
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uint32_t vbatt_req_err;
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uint32_t device_info_req;
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uint32_t device_info_resp;
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uint32_t device_info_err;
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u32 exit_power_save_req;
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u32 exit_power_save_resp;
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u32 exit_power_save_err;
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u32 enter_power_save_req;
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u32 enter_power_save_resp;
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u32 enter_power_save_err;
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u32 soc_wake_req;
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u32 soc_wake_resp;
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u32 soc_wake_err;
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u32 restart_level_req;
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u32 restart_level_resp;
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u32 restart_level_err;
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};
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#define WLFW_MAX_TIMESTAMP_LEN 32
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#define WLFW_MAX_BUILD_ID_LEN 128
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#define WLFW_MAX_NUM_MEMORY_REGIONS 2
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#define WLFW_FUNCTION_NAME_LEN 129
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#define WLFW_MAX_DATA_SIZE 6144
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#define WLFW_MAX_STR_LEN 16
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#define WLFW_MAX_NUM_CE 12
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#define WLFW_MAX_NUM_SVC 24
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#define WLFW_MAX_NUM_SHADOW_REG 24
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#define WLFW_MAX_HANG_EVENT_DATA_SIZE 400
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struct service_notifier_context {
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void *handle;
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uint32_t instance_id;
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char name[QMI_SERVREG_LOC_NAME_LENGTH_V01 + 1];
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};
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struct wlfw_rf_chip_info {
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uint32_t chip_id;
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uint32_t chip_family;
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};
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struct wlfw_rf_board_info {
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uint32_t board_id;
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};
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struct wlfw_fw_version_info {
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uint32_t fw_version;
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char fw_build_timestamp[WLFW_MAX_TIMESTAMP_LEN + 1];
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};
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struct icnss_mem_region_info {
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uint64_t reg_addr;
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uint32_t size;
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uint8_t secure_flag;
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};
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struct icnss_msi_user {
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char *name;
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int num_vectors;
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u32 base_vector;
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};
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struct icnss_msi_config {
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int total_vectors;
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int total_users;
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struct icnss_msi_user *users;
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};
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struct icnss_thermal_cdev {
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struct list_head tcdev_list;
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int tcdev_id;
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unsigned long curr_thermal_state;
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unsigned long max_thermal_state;
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struct device_node *dev_node;
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struct thermal_cooling_device *tcdev;
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};
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struct smp2p_out_info {
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unsigned short seq;
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unsigned int smem_bit;
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struct qcom_smem_state *smem_state;
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};
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struct icnss_dms_data {
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u8 mac_valid;
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u8 nv_mac_not_prov;
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u8 mac[QMI_WLFW_MAC_ADDR_SIZE_V01];
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};
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struct icnss_priv {
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uint32_t magic;
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struct platform_device *pdev;
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struct icnss_driver_ops *ops;
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struct ce_irq_list ce_irq_list[ICNSS_MAX_IRQ_REGISTRATIONS];
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struct list_head vreg_list;
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struct list_head clk_list;
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struct icnss_cpr_info cpr_info;
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unsigned long device_id;
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struct icnss_msi_config *msi_config;
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u32 msi_base_data;
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struct icnss_control_params ctrl_params;
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u8 cal_done;
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u8 use_prefix_path;
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u32 ce_irqs[ICNSS_MAX_IRQ_REGISTRATIONS];
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u32 srng_irqs[IWCN_MAX_IRQ_REGISTRATIONS];
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phys_addr_t mem_base_pa;
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void __iomem *mem_base_va;
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u32 mem_base_size;
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phys_addr_t mhi_state_info_pa;
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void __iomem *mhi_state_info_va;
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u32 mhi_state_info_size;
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struct iommu_domain *iommu_domain;
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dma_addr_t smmu_iova_start;
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size_t smmu_iova_len;
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dma_addr_t smmu_iova_ipa_start;
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dma_addr_t smmu_iova_ipa_current;
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size_t smmu_iova_ipa_len;
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struct qmi_handle qmi;
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struct qmi_handle qmi_dms;
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struct list_head event_list;
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struct list_head soc_wake_msg_list;
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spinlock_t event_lock;
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spinlock_t soc_wake_msg_lock;
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struct work_struct event_work;
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struct work_struct fw_recv_msg_work;
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struct work_struct soc_wake_msg_work;
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struct workqueue_struct *event_wq;
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struct workqueue_struct *soc_wake_wq;
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phys_addr_t msa_pa;
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phys_addr_t msi_addr_pa;
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dma_addr_t msi_addr_iova;
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uint32_t msa_mem_size;
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void *msa_va;
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unsigned long state;
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struct wlfw_rf_chip_info chip_info;
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uint32_t board_id;
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uint32_t soc_id;
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struct wlfw_fw_version_info fw_version_info;
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char fw_build_id[WLFW_MAX_BUILD_ID_LEN + 1];
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u32 pwr_pin_result;
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u32 phy_io_pin_result;
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u32 rf_pin_result;
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uint32_t nr_mem_region;
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struct icnss_mem_region_info
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mem_region[WLFW_MAX_NUM_MEMORY_REGIONS];
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struct dentry *root_dentry;
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spinlock_t on_off_lock;
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struct icnss_stats stats;
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struct work_struct service_notifier_work;
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struct service_notifier_context *service_notifier;
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struct notifier_block service_notifier_nb;
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int total_domains;
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struct notifier_block get_service_nb;
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void *modem_notify_handler;
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void *wpss_notify_handler;
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struct notifier_block modem_ssr_nb;
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struct notifier_block wpss_ssr_nb;
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uint32_t diag_reg_read_addr;
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uint32_t diag_reg_read_mem_type;
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uint32_t diag_reg_read_len;
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uint8_t *diag_reg_read_buf;
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atomic_t pm_count;
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struct ramdump_device *msa0_dump_dev;
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struct ramdump_device *m3_dump_dev_seg1;
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struct ramdump_device *m3_dump_dev_seg2;
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struct ramdump_device *m3_dump_dev_seg3;
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struct ramdump_device *m3_dump_dev_seg4;
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struct ramdump_device *m3_dump_dev_seg5;
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bool force_err_fatal;
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bool allow_recursive_recovery;
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bool early_crash_ind;
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u8 cause_for_rejuvenation;
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u8 requesting_sub_system;
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u16 line_number;
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struct mutex dev_lock;
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uint32_t fw_error_fatal_irq;
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uint32_t fw_early_crash_irq;
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struct smp2p_out_info smp2p_info;
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struct completion unblock_shutdown;
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struct adc_tm_param vph_monitor_params;
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struct adc_tm_chip *adc_tm_dev;
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struct iio_channel *channel;
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uint64_t vph_pwr;
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bool vbatt_supported;
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char function_name[WLFW_FUNCTION_NAME_LEN + 1];
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bool is_ssr;
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bool smmu_s1_enable;
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struct kobject *icnss_kobject;
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void *subsys;
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atomic_t is_shutdown;
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u32 qdss_mem_seg_len;
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struct icnss_fw_mem qdss_mem[QMI_WLFW_MAX_NUM_MEM_SEG];
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void *get_info_cb_ctx;
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int (*get_info_cb)(void *ctx, void *event, int event_len);
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atomic_t soc_wake_ref_count;
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phys_addr_t hang_event_data_pa;
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void __iomem *hang_event_data_va;
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uint16_t hang_event_data_len;
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void *hang_event_data;
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struct list_head icnss_tcdev_list;
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struct mutex tcdev_lock;
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bool is_chain1_supported;
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bool chain_reg_info_updated;
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u32 hw_trc_override;
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struct icnss_dms_data dms;
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u8 use_nv_mac;
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u32 wlan_en_delay_ms;
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bool psf_supported;
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struct notifier_block psf_nb;
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struct power_supply *batt_psy;
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int last_updated_voltage;
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struct work_struct soc_update_work;
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struct workqueue_struct *soc_update_wq;
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unsigned long device_config;
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struct timer_list recovery_timer;
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};
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struct icnss_reg_info {
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uint32_t mem_type;
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uint32_t reg_offset;
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uint32_t data_len;
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};
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void icnss_free_qdss_mem(struct icnss_priv *priv);
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char *icnss_driver_event_to_str(enum icnss_driver_event_type type);
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int icnss_call_driver_uevent(struct icnss_priv *priv,
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enum icnss_uevent uevent, void *data);
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int icnss_driver_event_post(struct icnss_priv *priv,
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enum icnss_driver_event_type type,
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u32 flags, void *data);
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void icnss_allow_recursive_recovery(struct device *dev);
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void icnss_disallow_recursive_recovery(struct device *dev);
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char *icnss_soc_wake_event_to_str(enum icnss_soc_wake_event_type type);
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int icnss_soc_wake_event_post(struct icnss_priv *priv,
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enum icnss_soc_wake_event_type type,
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u32 flags, void *data);
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int icnss_get_iova(struct icnss_priv *priv, u64 *addr, u64 *size);
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int icnss_get_iova_ipa(struct icnss_priv *priv, u64 *addr, u64 *size);
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int icnss_get_cpr_info(struct icnss_priv *priv);
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int icnss_update_cpr_info(struct icnss_priv *priv);
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void icnss_add_fw_prefix_name(struct icnss_priv *priv, char *prefix_name,
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char *name);
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void icnss_recovery_timeout_hdlr(struct timer_list *t);
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#endif
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