llcc supports 2 memory controllers in backend on certain systems. This patch adds support for dual memory controllers. Also fixed filter related changes in LLCC. Cleaned up the code for better code walk. Change-Id: Ie054d9182b20ec0811f117c2289aa857f0384baf Signed-off-by: Avinash Philip <avinashp@codeaurora.org>
298 lines
5.2 KiB
C
298 lines
5.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2019, The Linux Foundation. All rights reserved.
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*/
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#ifndef _SOC_QCOM_LLCC_EVENTS_H_
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#define _SOC_QCOM_LLCC_EVENTS_H_
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enum event_port_select {
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EVENT_PORT_FEAC,
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EVENT_PORT_FERC,
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EVENT_PORT_FEWC,
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EVENT_PORT_BEAC,
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EVENT_PORT_BERC,
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EVENT_PORT_TRP,
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EVENT_PORT_DRP,
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EVENT_PORT_PMGR,
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EVENT_PORT_BEAC1,
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EVENT_PORT_TENURE,
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EVENT_PORT_TLAT,
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};
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enum feac_events {
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FEAC_ANY_ACCESS,
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FEAC_READ_INCR,
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FEAC_WRITE_INCR,
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FEAC_WRITE_ORDERED,
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FEAC_READE_EXCL,
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FEAC_WRITE_EXCL,
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FEAC_CMO,
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FEAC_CMO_CLEAN,
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FEAC_CMO_INVAL,
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FEAC_CMO_CLEANINVAL,
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FEAC_CMO_DCPLD,
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FEAC_READ_NOALLOC,
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FEAC_WRITE_NOALLOC,
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FEAC_PREFETCH,
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FEAC_RD_BYTES,
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FEAC_RD_BEATS,
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FEAC_WR_BYTES,
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FEAC_WR_BEATS,
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FEAC_FC_READ,
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FEAC_EWD_ACCESS,
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FEAC_TCM_ACCESS,
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FEAC_GM_HIT,
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FEAC_GM_MISS,
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FEAC_GM_UNAVAILABLE,
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FEAC_XPU_ERROR,
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FEAC_READ_HAZARD,
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FEAC_WRITE_HAZARD,
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FEAC_GRANULE_READ,
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FEAC_GRANULE_WRITE,
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FEAC_RIFB_ALLOC,
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FEAC_WIFB_ALLOC,
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FEAC_RIFB_DEALLOC,
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FEAC_WIFB_DEALLOC,
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FEAC_RESERVED,
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FEAC_RESERVED1,
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FEAC_FEAC2TRP_LP_TX,
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FEAC_TRP_LP_BUSY,
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FEAC_FEAC2TRP_HP_TX,
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FEAC_TRP_HP_BUSY,
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FEAC_FEAC2FEWC_TX,
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FEAC_BEAC_LP_BUSY,
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FEAC_BEAC_HP_BUSY,
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FEAC_RIFB_FULL,
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FEAC_WIFB_FULL,
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FEAC_RD_CRDT_TX,
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FEAC_WR_CRDT_TX,
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FEAC_PROMOTION,
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FEAC_FEAC2TRP_LP_PRESSURE,
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FEAC_FEAC2TRP_HP_PRESSURE,
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FEAC_FEAC2FEWC_PRESSURE,
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FEAC_FEAC2BEAC_LP_PRESSURE,
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FEAC_FEAC2BEAC_HP_PRESSURE,
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FEAC_WR_THROUGH,
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};
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enum ferc_events {
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FERC_BERC_CMD,
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FERC_BERC_BEAT,
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FERC_DRP_CMD,
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FERC_DRP_BEAT,
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FERC_RD_CTRL_RSP_TX,
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FERC_WR_CTRL_RSP_TX,
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FERC_RD_DATA_TX,
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FERC_MISS_TRUMPS_HIT,
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FERC_HIT_TRUMPS_WRSP,
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FERC_RD_INTRA_RSP_IDLE,
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};
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enum fewc_events {
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FEWC_WR_CMD,
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FEWC_WR_DATA_BEAT,
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FEWC_WR_LAST,
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FEWC_WBUF_DEALLOC,
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FEWC_WR_HIT,
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FEWC_WR_MISS,
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FEWC_NC_RMW,
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FEWC_WR_DOWNGRADE,
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FEWC_BEAC_WR_CMD,
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FEWC_BEAC_WR_BEAT,
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FEWC_BEAC_RD_CMD,
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FEWC_BERC_FILL_BEAT,
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FEWC_DRP_WR_CMD,
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FEWC_DRP_WR_BEAT,
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FEWC_DRP_RD_BEAT,
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FEWC_TRP_TAG_LOOKUP,
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FEWC_TRP_TAG_UPDATE,
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FEWC_TRP_UNSTALL,
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FEWC_WBUFFS_FULL,
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FEWC_DRP_BUSY,
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FEWC_BEAC_WR_BUSY,
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FEWC_BEAC_RD_BUSY,
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FEWC_TRP_TAG_LOOKUP_BUSY,
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FEWC_TRP_TAG_UPDATE_BUSY,
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FEWC_C_RMW,
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FEWC_NC_ALLOC_RMW,
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FEWC_NC_NO_ALLOC_RMW,
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FEWC_NC_RMW_DEALLOC,
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FEWC_C_RMW_DEALLOC,
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FEWC_STALLED_BY_EVICT,
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};
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enum beac_events {
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BEAC_RD_TX,
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BEAC_WR_TX,
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BEAC_RD_GRANULE,
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BEAC_WR_GRANULE,
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BEAC_WR_BEAT_TX,
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BEAC_RD_CRDT_ZERO,
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BEAC_WR_CRDT_ZERO,
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BEAC_WDATA_CRDT_ZERO,
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BEAC_IFCMD_CRDT_ZERO,
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BEAC_IFWDATA_CRDT_ZERO,
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BEAC_PCT_ENTRY_ALLOC,
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BEAC_PCT_ENTRY_FREE,
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BEAC_PCT_FULL,
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BEAC_RD_PROMOTION_TX,
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BEAC_WR_PROMOTION_TX,
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BEAC_RD_PRESSURE_TX,
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BEAC_WR_PRESSURE_TX,
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};
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enum berc_events {
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BERC_RD_CMD,
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BERC_ERROR_CMD,
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BERC_PCT_ENTRY_DEALLOC,
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BERC_RD_RSP_RX,
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BERC_RD_RSP_BEAT_RX,
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BERC_RD_LA_RX,
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BERC_UNSTALL_RX,
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BERC_TX_RD_CMD,
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BERC_TX_ERR_CMD,
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BERC_TX_RD_BEAT,
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BERC_TX_ERR_BEAT,
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BERC_RESERVED,
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BERC_RESERVED1,
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BERC_CMO_RX,
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BERC_CMO_TX,
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BERC_DRP_WR_TX,
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BERC_DRP_WR_BEAT_TX,
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BERC_FEWC_WR_TX,
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BERC_FEWC_WR_BEAT_TX,
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BERC_LBUFFS_FULL,
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BERC_DRP_BUSY,
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BERC_FEWC_BUSY,
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BERC_LBUFF_STALLED,
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};
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enum trp_events {
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TRP_ANY_ACCESS,
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TRP_INCR_RD,
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TRP_INCR_WR,
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TRP_ANY_HIT,
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TRP_RD_HIT,
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TRP_WR_HIT,
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TRP_RD_MISS,
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TRP_WR_MISS,
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TRP_RD_HIT_MISS,
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TRP_WR_HIT_MISS,
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TRP_EVICT,
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TRP_GRANULE_EVICT,
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TRP_RD_EVICT,
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TRP_WR_EVICT,
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TRP_LINE_FILL,
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TRP_GRANULE_FILL,
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TRP_WSC_WRITE,
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TRP_WSC_EVICT,
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TRP_SUBCACHE_ACT,
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TRP_SUBCACHE_DEACT,
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TRP_RD_DEACTIVE_SUBCACHE,
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TRP_WR_DEACTIVE_SUBCACHE,
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TRP_INVALID_LINE_ALLOC,
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TRP_DEACTIVE_LINE_ALLOC,
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TRP_SELF_EVICTION_ALLOC,
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TRP_UC_SUBCACHE_ALLOC,
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TRP_FC_SELF_EVICTION_ALLOC,
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TRP_LP_SUBCACHE_VICTIM,
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TRP_OC_SUBCACHE_VICTIM,
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TRP_MRU_ROLLOVER,
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TRP_NC_DOWNGRADE,
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TRP_TAGRAM_CORR_ERR,
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TRP_TAGRAM_UNCORR_ERR,
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TRP_RD_MISS_FC,
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TRP_CPU_WRITE_EWD_LINE,
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TRP_CLIENT_WRITE_EWD_LINE,
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TRP_CLIENT_READ_EWD_LINE,
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TRP_CMO_I_EWD_LINE,
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TRP_CMO_I_DIRTY_LINE,
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TRP_DRP_RD_NOTIFICATION,
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TRP_DRP_WR_NOTIFICATION,
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TRP_LINEFILL_TAG_UPDATE,
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TRP_FEWC_TAG_UPDATE,
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TRP_ET_FULL,
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TRP_NAWT_FULL,
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TRP_HITQ_FULL,
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TRP_ET_ALLOC,
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TRP_ET_DEALLOC,
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TRP_NAWT_ALLOC,
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TRP_NAWT_DEALLOC,
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TRP_RD_REPLAY,
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TRP_WR_ECC_RD,
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TRP_ET_LP_FULL,
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TRP_ET_HP_FULL,
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TRP_SOEH,
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};
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enum drp_events {
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DRP_TRP_RD_NOTIFICATION,
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DRP_TRP_WR_NOTIFICATION,
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DRP_BIST_WR_NOTIFICATION,
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DRP_DRIE_WR_NOTIFICATION,
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DRP_ECC_CORR_ERR,
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DRP_ECC_UNCORR_ERR,
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DRP_FERC_RD_TX,
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DRP_FEWC_RD_TX,
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DRP_EVICT_LINE_TX,
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DRP_EVICT_GRANULE_TX,
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DRP_BIST_TX,
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DRP_FERC_RD_BEAT,
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DRP_FEWC_RD_BEAT,
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DRP_BIST_RD_BEAT,
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DRP_EVICT_RD_BEAT,
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DRP_BERC_WR_BEAT,
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DRP_FEWC_WR_BEAT,
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DRP_BIST_WR_BEAT,
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DRP_DRIE_WR_BEAT,
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DRP_BERC_UNSTALL,
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DRP_FEWC_UNSTALL,
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DRP_LB_RD,
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DRP_LB_WR,
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DRP_BANK_CONFLICT,
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DRP_FILL_TRUMPS_RD,
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DRP_RD_TRUMPS_WR,
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DRP_LB_SLP_RET,
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DRP_LB_SLP_NRET,
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DRP_LB_WAKEUP,
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DRP_TRP_EARLY_WAKEUP,
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DRP_PCB_IDLE,
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DRP_EVICT_RDFIFO_FULL,
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DRP_FEWC_RDFIFO_FULL,
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DRP_FERC_RDFIFO_FULL,
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DRP_FERC_RD,
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DRP_FEWC_RD,
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DRP_LINE_EVICT,
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DRP_GRANULE_EVICT,
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DRP_BIST_RD,
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DRP_FEWC_WR,
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DRP_LINE_FILL,
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DRP_GRANULE_FILL,
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DRP_BIST_WR,
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DRP_DRIE_WR,
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};
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enum pmgr_events {
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PMGR_Q_RUN_STATE,
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PMGR_Q_DENIED_STATE,
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PMGR_Q_STOPEED_TO_Q_RUN,
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PMGR_Q_RUN_TO_Q_FENCED,
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PMGR_Q_RUN_TO_Q_DENIED,
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PMGR_Q_DENIED_TO_Q_RUN,
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PMGR_Q_FENCED_TO_Q_STOPPED,
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PMGR_Q_FENCED_TO_Q_DENIED,
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};
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enum filter_type {
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SCID,
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MID,
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PROFILING_TAG,
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WAY_ID,
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OPCODE,
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CACHEALLOC,
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UNKNOWN,
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};
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#endif /* _SOC_QCOM_LLCC_EVENTS_H_ */
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