0a30d582d2
Add clock IDs for GCC/DISPCC/GPUCC for clients to be able to request for clocks from these clock controllers. Change-Id: I601af44801668ae76d5cd181051ae9ba7b0c6dc0 Signed-off-by: Saurabh Sahu <sausah@codeaurora.org>
42 lines
1.2 KiB
C
42 lines
1.2 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2020, The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_HOLI_H
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#define _DT_BINDINGS_CLK_QCOM_DISP_CC_HOLI_H
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/* DISP_CC clocks */
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#define DISP_CC_PLL0 0
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#define DISP_CC_MDSS_AHB_CLK 1
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#define DISP_CC_MDSS_AHB_CLK_SRC 2
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#define DISP_CC_MDSS_BYTE0_CLK 3
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#define DISP_CC_MDSS_BYTE0_CLK_SRC 4
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#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 5
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#define DISP_CC_MDSS_BYTE0_INTF_CLK 6
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#define DISP_CC_MDSS_ESC0_CLK 7
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#define DISP_CC_MDSS_ESC0_CLK_SRC 8
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#define DISP_CC_MDSS_MDP_CLK 9
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#define DISP_CC_MDSS_MDP_CLK_SRC 10
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#define DISP_CC_MDSS_MDP_LUT_CLK 11
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#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 12
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#define DISP_CC_MDSS_PCLK0_CLK 13
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#define DISP_CC_MDSS_PCLK0_CLK_SRC 14
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#define DISP_CC_MDSS_ROT_CLK 15
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#define DISP_CC_MDSS_ROT_CLK_SRC 16
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#define DISP_CC_MDSS_RSCC_AHB_CLK 17
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#define DISP_CC_MDSS_RSCC_VSYNC_CLK 18
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#define DISP_CC_MDSS_VSYNC_CLK 19
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#define DISP_CC_MDSS_VSYNC_CLK_SRC 20
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#define DISP_CC_SLEEP_CLK 21
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#define DISP_CC_XO_CLK 22
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/* DISP_CC power domains */
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#define DISP_CC_MDSS_CORE_GDSC 0
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/* DISP_CC resets */
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#define DISP_CC_MDSS_CORE_BCR 0
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#define DISP_CC_MDSS_RSCC_BCR 1
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#endif
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