fc8e50e349
The stuff below cleans up the code attempting to remap the whole cpm2_immr early, as well as places happily assuming that fact. This is more like the 2.4 legacy stuff, and is at least confusing and unclear now. To keep the world comfortable, a new mechanism is introduced: before accessing specific immr register/register set, one needs to map it, using cpm2_map(<reg>), for instance, access to CPM command register will look like volatile cpm_cpm2_t *cp = cpm2_map(im_cpm); keeping the code clear, yet without "already defined somewhere" cpm2_immr. So far, unmapping code is not implemented, but it's not a big deal to add it, if the whole idea makes sense. Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>
257 lines
6.1 KiB
C
257 lines
6.1 KiB
C
/*
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* Platform information definitions.
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*
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* Copied from arch/ppc/syslib/cpm2_pic.c with minor subsequent updates
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* to make in work in arch/powerpc/. Original (c) belongs to Dan Malek.
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*
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* Author: Vitaly Bordug <vbordug@ru.mvista.com>
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*
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* 1999-2001 (c) Dan Malek <dan@embeddedalley.com>
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* 2006 (c) MontaVista Software, Inc.
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*
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* This file is licensed under the terms of the GNU General Public License
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* version 2. This program is licensed "as is" without any warranty of any
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* kind, whether express or implied.
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*/
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/* The CPM2 internal interrupt controller. It is usually
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* the only interrupt controller.
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* There are two 32-bit registers (high/low) for up to 64
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* possible interrupts.
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*
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* Now, the fun starts.....Interrupt Numbers DO NOT MAP
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* in a simple arithmetic fashion to mask or pending registers.
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* That is, interrupt 4 does not map to bit position 4.
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* We create two tables, indexed by vector number, to indicate
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* which register to use and which bit in the register to use.
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*/
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#include <linux/stddef.h>
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#include <linux/init.h>
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#include <linux/sched.h>
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#include <linux/signal.h>
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#include <linux/irq.h>
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#include <asm/immap_cpm2.h>
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#include <asm/mpc8260.h>
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#include <asm/io.h>
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#include <asm/prom.h>
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#include "cpm2_pic.h"
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static struct device_node *cpm2_pic_node;
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static struct irq_host *cpm2_pic_host;
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#define NR_MASK_WORDS ((NR_IRQS + 31) / 32)
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static unsigned long ppc_cached_irq_mask[NR_MASK_WORDS];
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static const u_char irq_to_siureg[] = {
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1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 1, 1, 1, 1, 1, 1,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0,
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1, 1, 1, 1, 1, 1, 1, 1,
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1, 1, 1, 1, 1, 1, 1, 1,
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0, 0, 0, 0, 0, 0, 0, 0,
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0, 0, 0, 0, 0, 0, 0, 0
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};
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/* bit numbers do not match the docs, these are precomputed so the bit for
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* a given irq is (1 << irq_to_siubit[irq]) */
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static const u_char irq_to_siubit[] = {
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0, 15, 14, 13, 12, 11, 10, 9,
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8, 7, 6, 5, 4, 3, 2, 1,
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2, 1, 0, 14, 13, 12, 11, 10,
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9, 8, 7, 6, 5, 4, 3, 0,
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31, 30, 29, 28, 27, 26, 25, 24,
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23, 22, 21, 20, 19, 18, 17, 16,
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16, 17, 18, 19, 20, 21, 22, 23,
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24, 25, 26, 27, 28, 29, 30, 31,
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};
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static void cpm2_mask_irq(unsigned int irq_nr)
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{
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int bit, word;
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volatile uint *simr;
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irq_nr -= CPM_IRQ_OFFSET;
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bit = irq_to_siubit[irq_nr];
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word = irq_to_siureg[irq_nr];
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simr = &(cpm2_intctl->ic_simrh);
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ppc_cached_irq_mask[word] &= ~(1 << bit);
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simr[word] = ppc_cached_irq_mask[word];
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}
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static void cpm2_unmask_irq(unsigned int irq_nr)
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{
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int bit, word;
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volatile uint *simr;
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irq_nr -= CPM_IRQ_OFFSET;
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bit = irq_to_siubit[irq_nr];
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word = irq_to_siureg[irq_nr];
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simr = &(cpm2_intctl->ic_simrh);
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ppc_cached_irq_mask[word] |= 1 << bit;
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simr[word] = ppc_cached_irq_mask[word];
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}
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static void cpm2_mask_and_ack(unsigned int irq_nr)
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{
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int bit, word;
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volatile uint *simr, *sipnr;
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irq_nr -= CPM_IRQ_OFFSET;
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bit = irq_to_siubit[irq_nr];
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word = irq_to_siureg[irq_nr];
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simr = &(cpm2_intctl->ic_simrh);
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sipnr = &(cpm2_intctl->ic_sipnrh);
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ppc_cached_irq_mask[word] &= ~(1 << bit);
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simr[word] = ppc_cached_irq_mask[word];
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sipnr[word] = 1 << bit;
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}
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static void cpm2_end_irq(unsigned int irq_nr)
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{
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int bit, word;
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volatile uint *simr;
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if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))
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&& irq_desc[irq_nr].action) {
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irq_nr -= CPM_IRQ_OFFSET;
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bit = irq_to_siubit[irq_nr];
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word = irq_to_siureg[irq_nr];
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simr = &(cpm2_intctl->ic_simrh);
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ppc_cached_irq_mask[word] |= 1 << bit;
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simr[word] = ppc_cached_irq_mask[word];
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/*
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* Work around large numbers of spurious IRQs on PowerPC 82xx
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* systems.
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*/
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mb();
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}
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}
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static struct irq_chip cpm2_pic = {
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.typename = " CPM2 SIU ",
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.enable = cpm2_unmask_irq,
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.disable = cpm2_mask_irq,
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.unmask = cpm2_unmask_irq,
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.mask_ack = cpm2_mask_and_ack,
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.end = cpm2_end_irq,
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};
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int cpm2_get_irq(struct pt_regs *regs)
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{
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int irq;
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unsigned long bits;
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/* For CPM2, read the SIVEC register and shift the bits down
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* to get the irq number. */
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bits = cpm2_intctl->ic_sivec;
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irq = bits >> 26;
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if (irq == 0)
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return(-1);
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return irq+CPM_IRQ_OFFSET;
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}
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static int cpm2_pic_host_match(struct irq_host *h, struct device_node *node)
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{
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return cpm2_pic_node == NULL || cpm2_pic_node == node;
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}
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static int cpm2_pic_host_map(struct irq_host *h, unsigned int virq,
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irq_hw_number_t hw)
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{
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pr_debug("cpm2_pic_host_map(%d, 0x%lx)\n", virq, hw);
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get_irq_desc(virq)->status |= IRQ_LEVEL;
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set_irq_chip_and_handler(virq, &cpm2_pic, handle_level_irq);
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return 0;
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}
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static void cpm2_host_unmap(struct irq_host *h, unsigned int virq)
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{
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/* Make sure irq is masked in hardware */
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cpm2_mask_irq(virq);
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/* remove chip and handler */
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set_irq_chip_and_handler(virq, NULL, NULL);
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}
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static int cpm2_pic_host_xlate(struct irq_host *h, struct device_node *ct,
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u32 *intspec, unsigned int intsize,
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irq_hw_number_t *out_hwirq, unsigned int *out_flags)
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{
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static const unsigned char map_cpm2_senses[4] = {
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IRQ_TYPE_LEVEL_LOW,
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IRQ_TYPE_LEVEL_HIGH,
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IRQ_TYPE_EDGE_FALLING,
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IRQ_TYPE_EDGE_RISING,
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};
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*out_hwirq = intspec[0];
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if (intsize > 1 && intspec[1] < 4)
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*out_flags = map_cpm2_senses[intspec[1]];
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else
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*out_flags = IRQ_TYPE_NONE;
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return 0;
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}
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static struct irq_host_ops cpm2_pic_host_ops = {
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.match = cpm2_pic_host_match,
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.map = cpm2_pic_host_map,
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.unmap = cpm2_host_unmap,
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.xlate = cpm2_pic_host_xlate,
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};
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void cpm2_pic_init(struct device_node *node)
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{
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int i;
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/* Clear the CPM IRQ controller, in case it has any bits set
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* from the bootloader
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*/
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/* Mask out everything */
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cpm2_intctl->ic_simrh = 0x00000000;
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cpm2_intctl->ic_simrl = 0x00000000;
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wmb();
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/* Ack everything */
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cpm2_intctl->ic_sipnrh = 0xffffffff;
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cpm2_intctl->ic_sipnrl = 0xffffffff;
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wmb();
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/* Dummy read of the vector */
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i = cpm2_intctl->ic_sivec;
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rmb();
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/* Initialize the default interrupt mapping priorities,
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* in case the boot rom changed something on us.
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*/
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cpm2_intctl->ic_sicr = 0;
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cpm2_intctl->ic_scprrh = 0x05309770;
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cpm2_intctl->ic_scprrl = 0x05309770;
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/* create a legacy host */
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if (node)
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cpm2_pic_node = of_node_get(node);
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cpm2_pic_host = irq_alloc_host(IRQ_HOST_MAP_LINEAR, 64, &cpm2_pic_host_ops, 64);
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if (cpm2_pic_host == NULL) {
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printk(KERN_ERR "CPM2 PIC: failed to allocate irq host!\n");
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return;
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}
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}
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