7f3edee81f
This patch removes interrupt priority tables from the intc code. Optimal priority assignment varies with embedded application anyway, so keeping the interrupt priority tables together with cpu-specific code doesn't make sense. The function intc_set_priority() should be used instead to set the desired interrupt priority level. Signed-off-by: Magnus Damm <damm@igel.co.jp> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
609 lines
15 KiB
C
609 lines
15 KiB
C
/*
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* Shared interrupt handling code for IPR and INTC2 types of IRQs.
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*
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* Copyright (C) 2007 Magnus Damm
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*
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* Based on intc2.c and ipr.c
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*
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* Copyright (C) 1999 Niibe Yutaka & Takeshi Yaegashi
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* Copyright (C) 2000 Kazumoto Kojima
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* Copyright (C) 2001 David J. Mckay (david.mckay@st.com)
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* Copyright (C) 2003 Takashi Kusuda <kusuda-takashi@hitachi-ul.co.jp>
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* Copyright (C) 2005, 2006 Paul Mundt
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*/
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#include <linux/init.h>
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#include <linux/irq.h>
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#include <linux/module.h>
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#include <linux/io.h>
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#include <linux/interrupt.h>
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#include <linux/bootmem.h>
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#define _INTC_MK(fn, mode, addr_e, addr_d, width, shift) \
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((shift) | ((width) << 5) | ((fn) << 9) | ((mode) << 13) | \
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((addr_e) << 16) | ((addr_d << 24)))
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#define _INTC_SHIFT(h) (h & 0x1f)
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#define _INTC_WIDTH(h) ((h >> 5) & 0xf)
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#define _INTC_FN(h) ((h >> 9) & 0xf)
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#define _INTC_MODE(h) ((h >> 13) & 0x7)
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#define _INTC_ADDR_E(h) ((h >> 16) & 0xff)
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#define _INTC_ADDR_D(h) ((h >> 24) & 0xff)
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struct intc_handle_int {
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unsigned int irq;
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unsigned long handle;
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};
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struct intc_desc_int {
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unsigned long *reg;
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#ifdef CONFIG_SMP
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unsigned long *smp;
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#endif
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unsigned int nr_reg;
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struct intc_handle_int *prio;
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unsigned int nr_prio;
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struct intc_handle_int *sense;
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unsigned int nr_sense;
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struct irq_chip chip;
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};
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#ifdef CONFIG_SMP
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#define IS_SMP(x) x.smp
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#define INTC_REG(d, x, c) (d->reg[(x)] + ((d->smp[(x)] & 0xff) * c))
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#define SMP_NR(d, x) ((d->smp[(x)] >> 8) ? (d->smp[(x)] >> 8) : 1)
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#else
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#define IS_SMP(x) 0
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#define INTC_REG(d, x, c) (d->reg[(x)])
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#define SMP_NR(d, x) 1
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#endif
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static unsigned int intc_prio_level[NR_IRQS]; /* for now */
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static inline struct intc_desc_int *get_intc_desc(unsigned int irq)
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{
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struct irq_chip *chip = get_irq_chip(irq);
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return (void *)((char *)chip - offsetof(struct intc_desc_int, chip));
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}
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static inline unsigned int set_field(unsigned int value,
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unsigned int field_value,
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unsigned int handle)
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{
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unsigned int width = _INTC_WIDTH(handle);
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unsigned int shift = _INTC_SHIFT(handle);
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value &= ~(((1 << width) - 1) << shift);
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value |= field_value << shift;
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return value;
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}
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static void write_8(unsigned long addr, unsigned long h, unsigned long data)
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{
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ctrl_outb(set_field(0, data, h), addr);
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}
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static void write_16(unsigned long addr, unsigned long h, unsigned long data)
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{
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ctrl_outw(set_field(0, data, h), addr);
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}
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static void write_32(unsigned long addr, unsigned long h, unsigned long data)
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{
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ctrl_outl(set_field(0, data, h), addr);
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}
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static void modify_8(unsigned long addr, unsigned long h, unsigned long data)
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{
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ctrl_outb(set_field(ctrl_inb(addr), data, h), addr);
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}
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static void modify_16(unsigned long addr, unsigned long h, unsigned long data)
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{
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ctrl_outw(set_field(ctrl_inw(addr), data, h), addr);
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}
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static void modify_32(unsigned long addr, unsigned long h, unsigned long data)
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{
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ctrl_outl(set_field(ctrl_inl(addr), data, h), addr);
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}
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enum { REG_FN_ERR = 0, REG_FN_WRITE_BASE = 1, REG_FN_MODIFY_BASE = 5 };
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static void (*intc_reg_fns[])(unsigned long addr,
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unsigned long h,
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unsigned long data) = {
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[REG_FN_WRITE_BASE + 0] = write_8,
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[REG_FN_WRITE_BASE + 1] = write_16,
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[REG_FN_WRITE_BASE + 3] = write_32,
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[REG_FN_MODIFY_BASE + 0] = modify_8,
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[REG_FN_MODIFY_BASE + 1] = modify_16,
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[REG_FN_MODIFY_BASE + 3] = modify_32,
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};
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enum { MODE_ENABLE_REG = 0, /* Bit(s) set -> interrupt enabled */
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MODE_MASK_REG, /* Bit(s) set -> interrupt disabled */
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MODE_DUAL_REG, /* Two registers, set bit to enable / disable */
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MODE_PRIO_REG, /* Priority value written to enable interrupt */
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MODE_PCLR_REG, /* Above plus all bits set to disable interrupt */
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};
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static void intc_mode_field(unsigned long addr,
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unsigned long handle,
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void (*fn)(unsigned long,
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unsigned long,
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unsigned long),
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unsigned int irq)
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{
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fn(addr, handle, ((1 << _INTC_WIDTH(handle)) - 1));
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}
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static void intc_mode_zero(unsigned long addr,
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unsigned long handle,
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void (*fn)(unsigned long,
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unsigned long,
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unsigned long),
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unsigned int irq)
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{
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fn(addr, handle, 0);
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}
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static void intc_mode_prio(unsigned long addr,
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unsigned long handle,
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void (*fn)(unsigned long,
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unsigned long,
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unsigned long),
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unsigned int irq)
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{
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fn(addr, handle, intc_prio_level[irq]);
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}
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static void (*intc_enable_fns[])(unsigned long addr,
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unsigned long handle,
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void (*fn)(unsigned long,
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unsigned long,
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unsigned long),
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unsigned int irq) = {
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[MODE_ENABLE_REG] = intc_mode_field,
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[MODE_MASK_REG] = intc_mode_zero,
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[MODE_DUAL_REG] = intc_mode_field,
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[MODE_PRIO_REG] = intc_mode_prio,
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[MODE_PCLR_REG] = intc_mode_prio,
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};
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static void (*intc_disable_fns[])(unsigned long addr,
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unsigned long handle,
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void (*fn)(unsigned long,
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unsigned long,
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unsigned long),
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unsigned int irq) = {
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[MODE_ENABLE_REG] = intc_mode_zero,
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[MODE_MASK_REG] = intc_mode_field,
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[MODE_DUAL_REG] = intc_mode_field,
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[MODE_PRIO_REG] = intc_mode_zero,
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[MODE_PCLR_REG] = intc_mode_field,
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};
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static inline void _intc_enable(unsigned int irq, unsigned long handle)
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{
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struct intc_desc_int *d = get_intc_desc(irq);
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unsigned long addr;
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unsigned int cpu;
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for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_E(handle)); cpu++) {
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addr = INTC_REG(d, _INTC_ADDR_E(handle), cpu);
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intc_enable_fns[_INTC_MODE(handle)](addr, handle, intc_reg_fns\
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[_INTC_FN(handle)], irq);
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}
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}
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static void intc_enable(unsigned int irq)
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{
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_intc_enable(irq, (unsigned long)get_irq_chip_data(irq));
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}
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static void intc_disable(unsigned int irq)
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{
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struct intc_desc_int *d = get_intc_desc(irq);
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unsigned long handle = (unsigned long) get_irq_chip_data(irq);
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unsigned long addr;
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unsigned int cpu;
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for (cpu = 0; cpu < SMP_NR(d, _INTC_ADDR_D(handle)); cpu++) {
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addr = INTC_REG(d, _INTC_ADDR_D(handle), cpu);
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intc_disable_fns[_INTC_MODE(handle)](addr, handle,intc_reg_fns\
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[_INTC_FN(handle)], irq);
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}
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}
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static struct intc_handle_int *intc_find_irq(struct intc_handle_int *hp,
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unsigned int nr_hp,
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unsigned int irq)
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{
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int i;
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/* this doesn't scale well, but...
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*
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* this function should only be used for cerain uncommon
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* operations such as intc_set_priority() and intc_set_sense()
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* and in those rare cases performance doesn't matter that much.
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* keeping the memory footprint low is more important.
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*
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* one rather simple way to speed this up and still keep the
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* memory footprint down is to make sure the array is sorted
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* and then perform a bisect to lookup the irq.
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*/
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for (i = 0; i < nr_hp; i++) {
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if ((hp + i)->irq != irq)
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continue;
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return hp + i;
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}
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return NULL;
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}
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int intc_set_priority(unsigned int irq, unsigned int prio)
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{
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struct intc_desc_int *d = get_intc_desc(irq);
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struct intc_handle_int *ihp;
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if (!intc_prio_level[irq] || prio <= 1)
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return -EINVAL;
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ihp = intc_find_irq(d->prio, d->nr_prio, irq);
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if (ihp) {
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if (prio >= (1 << _INTC_WIDTH(ihp->handle)))
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return -EINVAL;
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intc_prio_level[irq] = prio;
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/*
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* only set secondary masking method directly
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* primary masking method is using intc_prio_level[irq]
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* priority level will be set during next enable()
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*/
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if (_INTC_FN(ihp->handle) != REG_FN_ERR)
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_intc_enable(irq, ihp->handle);
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}
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return 0;
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}
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#define VALID(x) (x | 0x80)
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static unsigned char intc_irq_sense_table[IRQ_TYPE_SENSE_MASK + 1] = {
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[IRQ_TYPE_EDGE_FALLING] = VALID(0),
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[IRQ_TYPE_EDGE_RISING] = VALID(1),
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[IRQ_TYPE_LEVEL_LOW] = VALID(2),
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[IRQ_TYPE_LEVEL_HIGH] = VALID(3),
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};
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static int intc_set_sense(unsigned int irq, unsigned int type)
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{
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struct intc_desc_int *d = get_intc_desc(irq);
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unsigned char value = intc_irq_sense_table[type & IRQ_TYPE_SENSE_MASK];
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struct intc_handle_int *ihp;
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unsigned long addr;
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if (!value)
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return -EINVAL;
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ihp = intc_find_irq(d->sense, d->nr_sense, irq);
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if (ihp) {
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addr = INTC_REG(d, _INTC_ADDR_E(ihp->handle), 0);
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intc_reg_fns[_INTC_FN(ihp->handle)](addr, ihp->handle, value);
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}
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return 0;
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}
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static unsigned int __init intc_get_reg(struct intc_desc_int *d,
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unsigned long address)
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{
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unsigned int k;
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for (k = 0; k < d->nr_reg; k++) {
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if (d->reg[k] == address)
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return k;
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}
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BUG();
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return 0;
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}
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static intc_enum __init intc_grp_id(struct intc_desc *desc,
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intc_enum enum_id)
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{
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struct intc_group *g = desc->groups;
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unsigned int i, j;
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for (i = 0; g && enum_id && i < desc->nr_groups; i++) {
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g = desc->groups + i;
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for (j = 0; g->enum_ids[j]; j++) {
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if (g->enum_ids[j] != enum_id)
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continue;
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return g->enum_id;
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}
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}
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return 0;
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}
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static unsigned int __init intc_mask_data(struct intc_desc *desc,
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struct intc_desc_int *d,
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intc_enum enum_id, int do_grps)
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{
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struct intc_mask_reg *mr = desc->mask_regs;
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unsigned int i, j, fn, mode;
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unsigned long reg_e, reg_d;
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for (i = 0; mr && enum_id && i < desc->nr_mask_regs; i++) {
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mr = desc->mask_regs + i;
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for (j = 0; j < ARRAY_SIZE(mr->enum_ids); j++) {
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if (mr->enum_ids[j] != enum_id)
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continue;
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if (mr->set_reg && mr->clr_reg) {
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fn = REG_FN_WRITE_BASE;
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mode = MODE_DUAL_REG;
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reg_e = mr->clr_reg;
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reg_d = mr->set_reg;
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} else {
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fn = REG_FN_MODIFY_BASE;
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if (mr->set_reg) {
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mode = MODE_ENABLE_REG;
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reg_e = mr->set_reg;
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reg_d = mr->set_reg;
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} else {
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mode = MODE_MASK_REG;
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reg_e = mr->clr_reg;
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reg_d = mr->clr_reg;
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}
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}
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fn += (mr->reg_width >> 3) - 1;
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return _INTC_MK(fn, mode,
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intc_get_reg(d, reg_e),
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intc_get_reg(d, reg_d),
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1,
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(mr->reg_width - 1) - j);
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}
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}
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if (do_grps)
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return intc_mask_data(desc, d, intc_grp_id(desc, enum_id), 0);
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return 0;
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}
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static unsigned int __init intc_prio_data(struct intc_desc *desc,
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struct intc_desc_int *d,
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intc_enum enum_id, int do_grps)
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{
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struct intc_prio_reg *pr = desc->prio_regs;
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unsigned int i, j, fn, mode, bit;
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unsigned long reg_e, reg_d;
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for (i = 0; pr && enum_id && i < desc->nr_prio_regs; i++) {
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pr = desc->prio_regs + i;
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for (j = 0; j < ARRAY_SIZE(pr->enum_ids); j++) {
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if (pr->enum_ids[j] != enum_id)
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continue;
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if (pr->set_reg && pr->clr_reg) {
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fn = REG_FN_WRITE_BASE;
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mode = MODE_PCLR_REG;
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reg_e = pr->set_reg;
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reg_d = pr->clr_reg;
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} else {
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fn = REG_FN_MODIFY_BASE;
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mode = MODE_PRIO_REG;
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if (!pr->set_reg)
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BUG();
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reg_e = pr->set_reg;
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reg_d = pr->set_reg;
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}
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fn += (pr->reg_width >> 3) - 1;
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bit = pr->reg_width - ((j + 1) * pr->field_width);
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BUG_ON(bit < 0);
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return _INTC_MK(fn, mode,
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intc_get_reg(d, reg_e),
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intc_get_reg(d, reg_d),
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pr->field_width, bit);
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}
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}
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if (do_grps)
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return intc_prio_data(desc, d, intc_grp_id(desc, enum_id), 0);
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return 0;
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}
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static unsigned int __init intc_sense_data(struct intc_desc *desc,
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struct intc_desc_int *d,
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intc_enum enum_id)
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{
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struct intc_sense_reg *sr = desc->sense_regs;
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unsigned int i, j, fn, bit;
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for (i = 0; sr && enum_id && i < desc->nr_sense_regs; i++) {
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sr = desc->sense_regs + i;
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for (j = 0; j < ARRAY_SIZE(sr->enum_ids); j++) {
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if (sr->enum_ids[j] != enum_id)
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continue;
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fn = REG_FN_MODIFY_BASE;
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fn += (sr->reg_width >> 3) - 1;
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bit = sr->reg_width - ((j + 1) * sr->field_width);
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BUG_ON(bit < 0);
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return _INTC_MK(fn, 0, intc_get_reg(d, sr->reg),
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0, sr->field_width, bit);
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}
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}
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return 0;
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}
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static void __init intc_register_irq(struct intc_desc *desc,
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struct intc_desc_int *d,
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intc_enum enum_id,
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unsigned int irq)
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{
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struct intc_handle_int *hp;
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unsigned int data[2], primary;
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/* Prefer single interrupt source bitmap over other combinations:
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* 1. bitmap, single interrupt source
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* 2. priority, single interrupt source
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* 3. bitmap, multiple interrupt sources (groups)
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* 4. priority, multiple interrupt sources (groups)
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*/
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data[0] = intc_mask_data(desc, d, enum_id, 0);
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data[1] = intc_prio_data(desc, d, enum_id, 0);
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primary = 0;
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if (!data[0] && data[1])
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primary = 1;
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data[0] = data[0] ? data[0] : intc_mask_data(desc, d, enum_id, 1);
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data[1] = data[1] ? data[1] : intc_prio_data(desc, d, enum_id, 1);
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if (!data[primary])
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primary ^= 1;
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BUG_ON(!data[primary]); /* must have primary masking method */
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disable_irq_nosync(irq);
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set_irq_chip_and_handler_name(irq, &d->chip,
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handle_level_irq, "level");
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set_irq_chip_data(irq, (void *)data[primary]);
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/* set priority level
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* - this needs to be at least 2 for 5-bit priorities on 7780
|
|
*/
|
|
intc_prio_level[irq] = 2;
|
|
|
|
/* enable secondary masking method if present */
|
|
if (data[!primary])
|
|
_intc_enable(irq, data[!primary]);
|
|
|
|
/* add irq to d->prio list if priority is available */
|
|
if (data[1]) {
|
|
hp = d->prio + d->nr_prio;
|
|
hp->irq = irq;
|
|
hp->handle = data[1];
|
|
|
|
if (primary) {
|
|
/*
|
|
* only secondary priority should access registers, so
|
|
* set _INTC_FN(h) = REG_FN_ERR for intc_set_priority()
|
|
*/
|
|
|
|
hp->handle &= ~_INTC_MK(0x0f, 0, 0, 0, 0, 0);
|
|
hp->handle |= _INTC_MK(REG_FN_ERR, 0, 0, 0, 0, 0);
|
|
}
|
|
d->nr_prio++;
|
|
}
|
|
|
|
/* add irq to d->sense list if sense is available */
|
|
data[0] = intc_sense_data(desc, d, enum_id);
|
|
if (data[0]) {
|
|
(d->sense + d->nr_sense)->irq = irq;
|
|
(d->sense + d->nr_sense)->handle = data[0];
|
|
d->nr_sense++;
|
|
}
|
|
|
|
/* irq should be disabled by default */
|
|
d->chip.mask(irq);
|
|
}
|
|
|
|
static unsigned int __init save_reg(struct intc_desc_int *d,
|
|
unsigned int cnt,
|
|
unsigned long value,
|
|
unsigned int smp)
|
|
{
|
|
if (value) {
|
|
d->reg[cnt] = value;
|
|
#ifdef CONFIG_SMP
|
|
d->smp[cnt] = smp;
|
|
#endif
|
|
return 1;
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
|
|
void __init register_intc_controller(struct intc_desc *desc)
|
|
{
|
|
unsigned int i, k, smp;
|
|
struct intc_desc_int *d;
|
|
|
|
d = alloc_bootmem(sizeof(*d));
|
|
|
|
d->nr_reg = desc->mask_regs ? desc->nr_mask_regs * 2 : 0;
|
|
d->nr_reg += desc->prio_regs ? desc->nr_prio_regs * 2 : 0;
|
|
d->nr_reg += desc->sense_regs ? desc->nr_sense_regs : 0;
|
|
|
|
d->reg = alloc_bootmem(d->nr_reg * sizeof(*d->reg));
|
|
#ifdef CONFIG_SMP
|
|
d->smp = alloc_bootmem(d->nr_reg * sizeof(*d->smp));
|
|
#endif
|
|
k = 0;
|
|
|
|
if (desc->mask_regs) {
|
|
for (i = 0; i < desc->nr_mask_regs; i++) {
|
|
smp = IS_SMP(desc->mask_regs[i]);
|
|
k += save_reg(d, k, desc->mask_regs[i].set_reg, smp);
|
|
k += save_reg(d, k, desc->mask_regs[i].clr_reg, smp);
|
|
}
|
|
}
|
|
|
|
if (desc->prio_regs) {
|
|
d->prio = alloc_bootmem(desc->nr_vectors * sizeof(*d->prio));
|
|
|
|
for (i = 0; i < desc->nr_prio_regs; i++) {
|
|
smp = IS_SMP(desc->prio_regs[i]);
|
|
k += save_reg(d, k, desc->prio_regs[i].set_reg, smp);
|
|
k += save_reg(d, k, desc->prio_regs[i].clr_reg, smp);
|
|
}
|
|
}
|
|
|
|
if (desc->sense_regs) {
|
|
d->sense = alloc_bootmem(desc->nr_vectors * sizeof(*d->sense));
|
|
|
|
for (i = 0; i < desc->nr_sense_regs; i++) {
|
|
k += save_reg(d, k, desc->sense_regs[i].reg, 0);
|
|
}
|
|
}
|
|
|
|
BUG_ON(k > 256); /* _INTC_ADDR_E() and _INTC_ADDR_D() are 8 bits */
|
|
|
|
d->chip.name = desc->name;
|
|
d->chip.mask = intc_disable;
|
|
d->chip.unmask = intc_enable;
|
|
d->chip.mask_ack = intc_disable;
|
|
d->chip.set_type = intc_set_sense;
|
|
|
|
for (i = 0; i < desc->nr_vectors; i++) {
|
|
struct intc_vect *vect = desc->vectors + i;
|
|
|
|
intc_register_irq(desc, d, vect->enum_id, evt2irq(vect->vect));
|
|
}
|
|
}
|