5f97f7f940
This adds support for the Atmel AVR32 architecture as well as the AT32AP7000 CPU and the AT32STK1000 development board. AVR32 is a new high-performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applications, with particular emphasis on low power consumption and high code density. The AVR32 architecture is not binary compatible with earlier 8-bit AVR architectures. The AVR32 architecture, including the instruction set, is described by the AVR32 Architecture Manual, available from http://www.atmel.com/dyn/resources/prod_documents/doc32000.pdf The Atmel AT32AP7000 is the first CPU implementing the AVR32 architecture. It features a 7-stage pipeline, 16KB instruction and data caches and a full Memory Management Unit. It also comes with a large set of integrated peripherals, many of which are shared with the AT91 ARM-based controllers from Atmel. Full data sheet is available from http://www.atmel.com/dyn/resources/prod_documents/doc32003.pdf while the CPU core implementation including caches and MMU is documented by the AVR32 AP Technical Reference, available from http://www.atmel.com/dyn/resources/prod_documents/doc32001.pdf Information about the AT32STK1000 development board can be found at http://www.atmel.com/dyn/products/tools_card.asp?tool_id=3918 including a BSP CD image with an earlier version of this patch, development tools (binaries and source/patches) and a root filesystem image suitable for booting from SD card. Alternatively, there's a preliminary "getting started" guide available at http://avr32linux.org/twiki/bin/view/Main/GettingStarted which provides links to the sources and patches you will need in order to set up a cross-compiling environment for avr32-linux. This patch, as well as the other patches included with the BSP and the toolchain patches, is actively supported by Atmel Corporation. [dmccr@us.ibm.com: Fix more pxx_page macro locations] [bunk@stusta.de: fix `make defconfig'] Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Signed-off-by: Adrian Bunk <bunk@stusta.de> Signed-off-by: Dave McCracken <dmccr@us.ibm.com> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Linus Torvalds <torvalds@osdl.org>
134 lines
2.8 KiB
C
134 lines
2.8 KiB
C
/*
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* Copyright (C) 2006 Atmel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/irq.h>
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#include <linux/platform_device.h>
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#include <asm/io.h>
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#include "intc.h"
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struct intc {
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void __iomem *regs;
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struct irq_chip chip;
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};
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extern struct platform_device at32_intc0_device;
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/*
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* TODO: We may be able to implement mask/unmask by setting IxM flags
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* in the status register.
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*/
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static void intc_mask_irq(unsigned int irq)
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{
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}
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static void intc_unmask_irq(unsigned int irq)
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{
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}
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static struct intc intc0 = {
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.chip = {
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.name = "intc",
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.mask = intc_mask_irq,
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.unmask = intc_unmask_irq,
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},
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};
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/*
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* All interrupts go via intc at some point.
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*/
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asmlinkage void do_IRQ(int level, struct pt_regs *regs)
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{
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struct irq_desc *desc;
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unsigned int irq;
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unsigned long status_reg;
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local_irq_disable();
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irq_enter();
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irq = intc_readl(&intc0, INTCAUSE0 - 4 * level);
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desc = irq_desc + irq;
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desc->handle_irq(irq, desc, regs);
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/*
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* Clear all interrupt level masks so that we may handle
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* interrupts during softirq processing. If this is a nested
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* interrupt, interrupts must stay globally disabled until we
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* return.
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*/
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status_reg = sysreg_read(SR);
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status_reg &= ~(SYSREG_BIT(I0M) | SYSREG_BIT(I1M)
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| SYSREG_BIT(I2M) | SYSREG_BIT(I3M));
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sysreg_write(SR, status_reg);
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irq_exit();
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}
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void __init init_IRQ(void)
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{
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extern void _evba(void);
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extern void irq_level0(void);
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struct resource *regs;
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struct clk *pclk;
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unsigned int i;
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u32 offset, readback;
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regs = platform_get_resource(&at32_intc0_device, IORESOURCE_MEM, 0);
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if (!regs) {
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printk(KERN_EMERG "intc: no mmio resource defined\n");
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goto fail;
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}
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pclk = clk_get(&at32_intc0_device.dev, "pclk");
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if (IS_ERR(pclk)) {
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printk(KERN_EMERG "intc: no clock defined\n");
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goto fail;
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}
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clk_enable(pclk);
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intc0.regs = ioremap(regs->start, regs->end - regs->start + 1);
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if (!intc0.regs) {
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printk(KERN_EMERG "intc: failed to map registers (0x%08lx)\n",
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(unsigned long)regs->start);
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goto fail;
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}
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/*
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* Initialize all interrupts to level 0 (lowest priority). The
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* priority level may be changed by calling
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* irq_set_priority().
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*
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*/
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offset = (unsigned long)&irq_level0 - (unsigned long)&_evba;
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for (i = 0; i < NR_INTERNAL_IRQS; i++) {
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intc_writel(&intc0, INTPR0 + 4 * i, offset);
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readback = intc_readl(&intc0, INTPR0 + 4 * i);
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if (readback == offset)
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set_irq_chip_and_handler(i, &intc0.chip,
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handle_simple_irq);
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}
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/* Unmask all interrupt levels */
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sysreg_write(SR, (sysreg_read(SR)
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& ~(SR_I3M | SR_I2M | SR_I1M | SR_I0M)));
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return;
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fail:
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panic("Interrupt controller initialization failed!\n");
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}
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