1da177e4c3
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
518 lines
11 KiB
ArmAsm
518 lines
11 KiB
ArmAsm
/*
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* linux/arch/arm26/boot/compressed/head.S
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*
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* Copyright (C) 1996-2002 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/config.h>
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#include <linux/linkage.h>
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/*
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* Debugging stuff
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*
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* Note that these macros must not contain any code which is not
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* 100% relocatable. Any attempt to do so will result in a crash.
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* Please select one of the following when turning on debugging.
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*/
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.macro kputc,val
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mov r0, \val
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bl putc
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.endm
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.macro kphex,val,len
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mov r0, \val
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mov r1, #\len
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bl phex
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.endm
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.macro debug_reloc_start
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.endm
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.macro debug_reloc_end
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.endm
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.section ".start", #alloc, #execinstr
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/*
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* sort out different calling conventions
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*/
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.align
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start:
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.type start,#function
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.rept 8
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mov r0, r0
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.endr
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b 1f
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.word 0x016f2818 @ Magic numbers to help the loader
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.word start @ absolute load/run zImage address
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.word _edata @ zImage end address
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1: mov r7, r1 @ save architecture ID
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mov r8, #0 @ save r0
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teqp pc, #0x0c000003 @ turn off interrupts
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.text
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adr r0, LC0
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ldmia r0, {r1, r2, r3, r4, r5, r6, ip, sp}
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subs r0, r0, r1 @ calculate the delta offset
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teq r0, #0 @ if delta is zero, we're
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beq not_relocated @ running at the address we
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@ were linked at.
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add r2, r2, r0 @ different address, so we
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add r3, r3, r0 @ need to fix up various
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add r5, r5, r0 @ pointers.
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add r6, r6, r0
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add ip, ip, r0
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add sp, sp, r0
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1: ldr r1, [r6, #0] @ relocate entries in the GOT
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add r1, r1, r0 @ table. This fixes up the
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str r1, [r6], #4 @ C references.
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cmp r6, ip
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blo 1b
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not_relocated: mov r0, #0
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1: str r0, [r2], #4 @ clear bss
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str r0, [r2], #4
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str r0, [r2], #4
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str r0, [r2], #4
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cmp r2, r3
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blo 1b
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bl cache_on
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mov r1, sp @ malloc space above stack
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add r2, sp, #0x10000 @ 64k max
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/*
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* Check to see if we will overwrite ourselves.
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* r4 = final kernel address
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* r5 = start of this image
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* r2 = end of malloc space (and therefore this image)
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* We basically want:
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* r4 >= r2 -> OK
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* r4 + image length <= r5 -> OK
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*/
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cmp r4, r2
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bhs wont_overwrite
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add r0, r4, #4096*1024 @ 4MB largest kernel size
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cmp r0, r5
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bls wont_overwrite
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mov r5, r2 @ decompress after malloc space
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mov r0, r5
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mov r3, r7
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bl decompress_kernel
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add r0, r0, #127
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bic r0, r0, #127 @ align the kernel length
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/*
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* r0 = decompressed kernel length
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* r1-r3 = unused
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* r4 = kernel execution address
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* r5 = decompressed kernel start
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* r6 = processor ID
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* r7 = architecture ID
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* r8-r14 = unused
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*/
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add r1, r5, r0 @ end of decompressed kernel
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adr r2, reloc_start
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ldr r3, LC1
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add r3, r2, r3
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1: ldmia r2!, {r8 - r13} @ copy relocation code
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stmia r1!, {r8 - r13}
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ldmia r2!, {r8 - r13}
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stmia r1!, {r8 - r13}
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cmp r2, r3
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blo 1b
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bl cache_clean_flush
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add pc, r5, r0 @ call relocation code
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/*
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* We're not in danger of overwriting ourselves. Do this the simple way.
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*
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* r4 = kernel execution address
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* r7 = architecture ID
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*/
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wont_overwrite: mov r0, r4
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mov r3, r7
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bl decompress_kernel
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b call_kernel
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.type LC0, #object
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LC0: .word LC0 @ r1
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.word __bss_start @ r2
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.word _end @ r3
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.word _load_addr @ r4
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.word _start @ r5
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.word _got_start @ r6
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.word _got_end @ ip
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.word user_stack+4096 @ sp
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LC1: .word reloc_end - reloc_start
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.size LC0, . - LC0
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/*
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* Turn on the cache. We need to setup some page tables so that we
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* can have both the I and D caches on.
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*
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* We place the page tables 16k down from the kernel execution address,
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* and we hope that nothing else is using it. If we're using it, we
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* will go pop!
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*
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* On entry,
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* r4 = kernel execution address
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* r6 = processor ID
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* r7 = architecture number
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* r8 = run-time address of "start"
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* On exit,
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* r1, r2, r3, r8, r9, r12 corrupted
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* This routine must preserve:
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* r4, r5, r6, r7
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*/
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.align 5
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cache_on: mov r3, #8 @ cache_on function
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b call_cache_fn
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__setup_mmu: sub r3, r4, #16384 @ Page directory size
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bic r3, r3, #0xff @ Align the pointer
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bic r3, r3, #0x3f00
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/*
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* Initialise the page tables, turning on the cacheable and bufferable
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* bits for the RAM area only.
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*/
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mov r0, r3
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mov r8, r0, lsr #18
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mov r8, r8, lsl #18 @ start of RAM
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add r9, r8, #0x10000000 @ a reasonable RAM size
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mov r1, #0x12
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orr r1, r1, #3 << 10
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add r2, r3, #16384
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1: cmp r1, r8 @ if virt > start of RAM
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orrhs r1, r1, #0x0c @ set cacheable, bufferable
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cmp r1, r9 @ if virt > end of RAM
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bichs r1, r1, #0x0c @ clear cacheable, bufferable
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str r1, [r0], #4 @ 1:1 mapping
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add r1, r1, #1048576
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teq r0, r2
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bne 1b
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/*
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* If ever we are running from Flash, then we surely want the cache
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* to be enabled also for our execution instance... We map 2MB of it
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* so there is no map overlap problem for up to 1 MB compressed kernel.
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* If the execution is in RAM then we would only be duplicating the above.
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*/
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mov r1, #0x1e
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orr r1, r1, #3 << 10
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mov r2, pc, lsr #20
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orr r1, r1, r2, lsl #20
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add r0, r3, r2, lsl #2
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str r1, [r0], #4
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add r1, r1, #1048576
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str r1, [r0]
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mov pc, lr
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__armv4_cache_on:
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mov r12, lr
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bl __setup_mmu
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mov r0, #0
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mcr p15, 0, r0, c7, c10, 4 @ drain write buffer
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mcr p15, 0, r0, c8, c7, 0 @ flush I,D TLBs
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mrc p15, 0, r0, c1, c0, 0 @ read control reg
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orr r0, r0, #0x1000 @ I-cache enable
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orr r0, r0, #0x0030
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b __common_cache_on
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__arm6_cache_on:
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mov r12, lr
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bl __setup_mmu
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mov r0, #0
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mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
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mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
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mov r0, #0x30
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__common_cache_on:
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#ifndef DEBUG
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orr r0, r0, #0x000d @ Write buffer, mmu
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#endif
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mov r1, #-1
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mcr p15, 0, r3, c2, c0, 0 @ load page table pointer
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mcr p15, 0, r1, c3, c0, 0 @ load domain access control
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mcr p15, 0, r0, c1, c0, 0 @ load control register
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mov pc, r12
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/*
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* All code following this line is relocatable. It is relocated by
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* the above code to the end of the decompressed kernel image and
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* executed there. During this time, we have no stacks.
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*
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* r0 = decompressed kernel length
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* r1-r3 = unused
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* r4 = kernel execution address
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* r5 = decompressed kernel start
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* r6 = processor ID
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* r7 = architecture ID
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* r8-r14 = unused
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*/
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.align 5
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reloc_start: add r8, r5, r0
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debug_reloc_start
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mov r1, r4
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1:
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.rept 4
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ldmia r5!, {r0, r2, r3, r9 - r13} @ relocate kernel
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stmia r1!, {r0, r2, r3, r9 - r13}
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.endr
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cmp r5, r8
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blo 1b
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debug_reloc_end
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call_kernel: bl cache_clean_flush
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bl cache_off
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mov r0, #0
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mov r1, r7 @ restore architecture number
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mov pc, r4 @ call kernel
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/*
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* Here follow the relocatable cache support functions for the
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* various processors. This is a generic hook for locating an
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* entry and jumping to an instruction at the specified offset
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* from the start of the block. Please note this is all position
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* independent code.
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*
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* r1 = corrupted
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* r2 = corrupted
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* r3 = block offset
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* r6 = corrupted
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* r12 = corrupted
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*/
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call_cache_fn: adr r12, proc_types
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mrc p15, 0, r6, c0, c0 @ get processor ID
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1: ldr r1, [r12, #0] @ get value
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ldr r2, [r12, #4] @ get mask
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eor r1, r1, r6 @ (real ^ match)
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tst r1, r2 @ & mask
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addeq pc, r12, r3 @ call cache function
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add r12, r12, #4*5
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b 1b
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/*
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* Table for cache operations. This is basically:
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* - CPU ID match
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* - CPU ID mask
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* - 'cache on' method instruction
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* - 'cache off' method instruction
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* - 'cache flush' method instruction
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*
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* We match an entry using: ((real_id ^ match) & mask) == 0
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*
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* Writethrough caches generally only need 'on' and 'off'
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* methods. Writeback caches _must_ have the flush method
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* defined.
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*/
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.type proc_types,#object
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proc_types:
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.word 0x41560600 @ ARM6/610
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.word 0xffffffe0
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b __arm6_cache_off @ works, but slow
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b __arm6_cache_off
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mov pc, lr
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@ b __arm6_cache_on @ untested
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@ b __arm6_cache_off
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@ b __armv3_cache_flush
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.word 0x41007000 @ ARM7/710
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.word 0xfff8fe00
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b __arm7_cache_off
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b __arm7_cache_off
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mov pc, lr
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.word 0x41807200 @ ARM720T (writethrough)
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.word 0xffffff00
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b __armv4_cache_on
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b __armv4_cache_off
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mov pc, lr
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.word 0x41129200 @ ARM920T
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.word 0xff00fff0
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b __armv4_cache_on
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b __armv4_cache_off
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b __armv4_cache_flush
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.word 0x4401a100 @ sa110 / sa1100
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.word 0xffffffe0
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b __armv4_cache_on
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b __armv4_cache_off
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b __armv4_cache_flush
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.word 0x6901b110 @ sa1110
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.word 0xfffffff0
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b __armv4_cache_on
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b __armv4_cache_off
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b __armv4_cache_flush
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.word 0x69050000 @ xscale
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.word 0xffff0000
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b __armv4_cache_on
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b __armv4_cache_off
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b __armv4_cache_flush
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.word 0 @ unrecognised type
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.word 0
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mov pc, lr
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mov pc, lr
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mov pc, lr
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.size proc_types, . - proc_types
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/*
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* Turn off the Cache and MMU. ARMv3 does not support
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* reading the control register, but ARMv4 does.
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*
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* On entry, r6 = processor ID
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* On exit, r0, r1, r2, r3, r12 corrupted
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* This routine must preserve: r4, r6, r7
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*/
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.align 5
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cache_off: mov r3, #12 @ cache_off function
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b call_cache_fn
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__armv4_cache_off:
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mrc p15, 0, r0, c1, c0
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bic r0, r0, #0x000d
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mcr p15, 0, r0, c1, c0 @ turn MMU and cache off
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mov r0, #0
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mcr p15, 0, r0, c7, c7 @ invalidate whole cache v4
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mcr p15, 0, r0, c8, c7 @ invalidate whole TLB v4
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mov pc, lr
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__arm6_cache_off:
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mov r0, #0x00000030 @ ARM6 control reg.
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b __armv3_cache_off
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__arm7_cache_off:
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mov r0, #0x00000070 @ ARM7 control reg.
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b __armv3_cache_off
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__armv3_cache_off:
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mcr p15, 0, r0, c1, c0, 0 @ turn MMU and cache off
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mov r0, #0
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mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
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mcr p15, 0, r0, c5, c0, 0 @ invalidate whole TLB v3
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mov pc, lr
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/*
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* Clean and flush the cache to maintain consistency.
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*
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* On entry,
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* r6 = processor ID
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* On exit,
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* r1, r2, r3, r12 corrupted
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* This routine must preserve:
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* r0, r4, r5, r6, r7
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*/
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.align 5
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cache_clean_flush:
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mov r3, #16
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b call_cache_fn
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__armv4_cache_flush:
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bic r1, pc, #31
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add r2, r1, #65536 @ 2x the largest dcache size
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1: ldr r12, [r1], #32 @ s/w flush D cache
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teq r1, r2
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bne 1b
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mcr p15, 0, r1, c7, c7, 0 @ flush I cache
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mcr p15, 0, r1, c7, c10, 4 @ drain WB
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mov pc, lr
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__armv3_cache_flush:
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mov r1, #0
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mcr p15, 0, r0, c7, c0, 0 @ invalidate whole cache v3
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mov pc, lr
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/*
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* Various debugging routines for printing hex characters and
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* memory, which again must be relocatable.
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*/
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#ifdef DEBUG
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.type phexbuf,#object
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phexbuf: .space 12
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.size phexbuf, . - phexbuf
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phex: adr r3, phexbuf
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mov r2, #0
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strb r2, [r3, r1]
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1: subs r1, r1, #1
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movmi r0, r3
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bmi puts
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and r2, r0, #15
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mov r0, r0, lsr #4
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cmp r2, #10
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addge r2, r2, #7
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add r2, r2, #'0'
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strb r2, [r3, r1]
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b 1b
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puts: loadsp r3
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1: ldrb r2, [r0], #1
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teq r2, #0
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moveq pc, lr
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2: writeb r2
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mov r1, #0x00020000
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3: subs r1, r1, #1
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bne 3b
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teq r2, #'\n'
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moveq r2, #'\r'
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beq 2b
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teq r0, #0
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bne 1b
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mov pc, lr
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putc:
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mov r2, r0
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mov r0, #0
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loadsp r3
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b 2b
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memdump: mov r12, r0
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mov r10, lr
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mov r11, #0
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2: mov r0, r11, lsl #2
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add r0, r0, r12
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mov r1, #8
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bl phex
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mov r0, #':'
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bl putc
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1: mov r0, #' '
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bl putc
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ldr r0, [r12, r11, lsl #2]
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mov r1, #8
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bl phex
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and r0, r11, #7
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teq r0, #3
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moveq r0, #' '
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bleq putc
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and r0, r11, #7
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add r11, r11, #1
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teq r0, #7
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bne 1b
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mov r0, #'\n'
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bl putc
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cmp r11, #64
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blt 2b
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mov pc, r10
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#endif
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reloc_end:
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.align
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.section ".stack", "aw"
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user_stack: .space 4096
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