7090c5fd8d
qcacld-3.0: Initial snapshot of ihelium wlan driver to match code-scanned SU Release 5.0.0.139. This is open-source version of wlan for next Android release. Change-Id: Icf598ca97da74f84bea607e4e902d1889806f507
674 lines
26 KiB
C
674 lines
26 KiB
C
/*
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* Copyright (c) 2012-2015 The Linux Foundation. All rights reserved.
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*
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* Previously licensed under the ISC license by Qualcomm Atheros, Inc.
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*
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*
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* Permission to use, copy, modify, and/or distribute this software for
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* any purpose with or without fee is hereby granted, provided that the
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* above copyright notice and this permission notice appear in all
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* copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
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* WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
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* AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
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* DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
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* PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
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* TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
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* PERFORMANCE OF THIS SOFTWARE.
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*/
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/*
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* This file was originally distributed by Qualcomm Atheros, Inc.
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* under proprietary terms before Copyright ownership was assigned
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* to the Linux Foundation.
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*/
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#ifndef __TARGADDRS_H__
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#define __TARGADDRS_H__
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#if defined(ATH_TARGET)
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#include "soc_addrs.h"
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#endif
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#if !defined(ATH_TARGET)
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#include "athstartpack.h"
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#endif
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/*
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* SOC option bits, to enable/disable various features.
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* By default, all option bits are 0.
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* AR6004: These bits can be set in LOCAL_SCRATCH register 0.
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* AR9888: These bits can be set in soc_core register SCRATCH_0.
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*/
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#define SOC_OPTION_BMI_DISABLE 0x01 /* Disable BMI comm with Host */
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#define SOC_OPTION_SERIAL_ENABLE 0x02 /* Enable serial port msgs */
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#define SOC_OPTION_WDT_DISABLE 0x04 /* WatchDog Timer override */
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#define SOC_OPTION_SLEEP_DISABLE 0x08 /* Disable system sleep */
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#define SOC_OPTION_STOP_BOOT 0x10 /* Stop boot processes (for ATE) */
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#define SOC_OPTION_ENABLE_NOANI 0x20 /* Operate without ANI */
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#define SOC_OPTION_DSET_DISABLE 0x40 /* Ignore DataSets */
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#define SOC_OPTION_IGNORE_FLASH 0x80 /* Ignore flash during bootup */
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/*
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* xxx_HOST_INTEREST_ADDRESS is the address in Target RAM of the
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* host_interest structure. It must match the address of the _host_interest
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* symbol (see linker script).
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*
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* Host Interest is shared between Host and Target in order to coordinate
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* between the two, and is intended to remain constant (with additions only
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* at the end) across software releases.
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*
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* All addresses are available here so that it's possible to
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* write a single binary that works with all Target Types.
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* May be used in assembler code as well as C.
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*/
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#define AR6002_HOST_INTEREST_ADDRESS 0x00500400
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#define AR6003_HOST_INTEREST_ADDRESS 0x00540600
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#define AR6004_HOST_INTEREST_ADDRESS 0x00400800
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#define AR9888_HOST_INTEREST_ADDRESS 0x00400800
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#define AR900B_HOST_INTEREST_ADDRESS 0x00400800
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#define AR6320_HOST_INTEREST_ADDRESS 0x00400800
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#define QCA6180_HOST_INTEREST_ADDRESS 0x005d96a0
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#define AR6004_SOC_RESET_ADDRESS 0X00004000
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#define AR6004_SOC_RESET_CPU_INIT_RESET_MASK 0X00000800
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#if defined(AR6006_MEMORY_NEW_ARCH)
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#define AR6006_HOST_INTEREST_ADDRESS 0x00428800
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#else
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#define AR6006_HOST_INTEREST_ADDRESS 0x00400800
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#endif
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#define AR6006_SOC_RESET_ADDRESS 0X00004000
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#define AR6006_SOC_RESET_CPU_INIT_RESET_MASK 0X00000800
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#define HOST_INTEREST_MAX_SIZE 0x200
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#if !defined(__ASSEMBLER__)
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struct register_dump_s;
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struct dbglog_hdr_s;
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/*
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* These are items that the Host may need to access
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* via BMI or via the Diagnostic Window. The position
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* of items in this structure must remain constant
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* across firmware revisions!
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*
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* Types for each item must be fixed size across
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* target and host platforms.
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*
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* More items may be added at the end.
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*/
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PREPACK64 struct host_interest_s {
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/*
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* Pointer to application-defined area, if any.
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* Set by Target application during startup.
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*/
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A_UINT32 hi_app_host_interest; /* 0x00 */
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/* Pointer to register dump area, valid after Target crash. */
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A_UINT32 hi_failure_state; /* 0x04 */
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/* Pointer to debug logging header */
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A_UINT32 hi_dbglog_hdr; /* 0x08 */
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/* Save SW ROM version */
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A_UINT32 hi_sw_rom_version; /* 0x0c */
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/*
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* General-purpose flag bits, similar to SOC_OPTION_* flags.
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* Can be used by application rather than by OS.
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*/
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A_UINT32 hi_option_flag; /* 0x10 */
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/*
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* Boolean that determines whether or not to
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* display messages on the serial port.
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*/
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A_UINT32 hi_serial_enable; /* 0x14 */
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/* Start address of DataSet index, if any */
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A_UINT32 hi_dset_list_head; /* 0x18 */
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/* Override Target application start address */
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A_UINT32 hi_app_start; /* 0x1c */
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/* Clock and voltage tuning */
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A_UINT32 hi_skip_clock_init; /* 0x20 */
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A_UINT32 hi_core_clock_setting; /* 0x24 */
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A_UINT32 hi_cpu_clock_setting; /* 0x28 */
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A_UINT32 hi_system_sleep_setting; /* 0x2c */
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A_UINT32 hi_xtal_control_setting; /* 0x30 */
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A_UINT32 hi_pll_ctrl_setting_24ghz; /* 0x34 */
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A_UINT32 hi_pll_ctrl_setting_5ghz; /* 0x38 */
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A_UINT32 hi_ref_voltage_trim_setting; /* 0x3c */
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A_UINT32 hi_clock_info; /* 0x40 */
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/* Host uses BE CPU or not */
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A_UINT32 hi_be; /* 0x44 */
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A_UINT32 hi_stack; /* normal stack *//* 0x48 */
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A_UINT32 hi_err_stack; /* error stack *//* 0x4c */
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A_UINT32 hi_desired_cpu_speed_hz; /* 0x50 */
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/* Pointer to Board Data */
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A_UINT32 hi_board_data; /* 0x54 */
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/*
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* Indication of Board Data state:
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* 0: board data is not yet initialized.
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* 1: board data is initialized; unknown size
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* >1: number of bytes of initialized board data (varies with board type)
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*/
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A_UINT32 hi_board_data_initialized; /* 0x58 */
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A_UINT32 hi_dset_RAM_index_table; /* 0x5c */
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A_UINT32 hi_desired_baud_rate; /* 0x60 */
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A_UINT32 hi_dbglog_config; /* 0x64 */
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A_UINT32 hi_end_RAM_reserve_sz; /* 0x68 */
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A_UINT32 hi_mbox_io_block_sz; /* 0x6c */
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A_UINT32 hi_num_bpatch_streams; /* 0x70 -- unused */
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A_UINT32 hi_mbox_isr_yield_limit; /* 0x74 */
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A_UINT32 hi_refclk_hz; /* 0x78 */
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A_UINT32 hi_ext_clk_detected; /* 0x7c */
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A_UINT32 hi_dbg_uart_txpin; /* 0x80 */
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A_UINT32 hi_dbg_uart_rxpin; /* 0x84 */
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A_UINT32 hi_hci_uart_baud; /* 0x88 */
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A_UINT32 hi_hci_uart_pin_assignments; /* 0x8C */
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/* NOTE: byte [0] = tx pin, [1] = rx pin, [2] = rts pin, [3] = cts pin */
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A_UINT32 hi_hci_uart_baud_scale_val; /* 0x90 */
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A_UINT32 hi_hci_uart_baud_step_val; /* 0x94 */
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A_UINT32 hi_allocram_start; /* 0x98 */
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A_UINT32 hi_allocram_sz; /* 0x9c */
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A_UINT32 hi_hci_bridge_flags; /* 0xa0 */
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A_UINT32 hi_hci_uart_support_pins; /* 0xa4 */
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/* NOTE: byte [0] = RESET pin (bit 7 is polarity), bytes[1]..bytes[3] are for future use */
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A_UINT32 hi_hci_uart_pwr_mgmt_params; /* 0xa8 */
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/* 0xa8 - [1]: 0 = UART FC active low, 1 = UART FC active high
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* [31:16]: wakeup timeout in ms
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*/
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/* Pointer to extended board Data */
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A_UINT32 hi_board_ext_data; /* 0xac */
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A_UINT32 hi_board_ext_data_config; /* 0xb0 */
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/*
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* Bit [0] : valid
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* Bit[31:16: size
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*/
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/*
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* hi_reset_flag is used to do some stuff when target reset.
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* such as restore app_start after warm reset or
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* preserve host Interest area, or preserve ROM data, literals etc.
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*/
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A_UINT32 hi_reset_flag; /* 0xb4 */
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/* indicate hi_reset_flag is valid */
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A_UINT32 hi_reset_flag_valid; /* 0xb8 */
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A_UINT32 hi_hci_uart_pwr_mgmt_params_ext; /* 0xbc */
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/* 0xbc - [31:0]: idle timeout in ms
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*/
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/* ACS flags */
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A_UINT32 hi_acs_flags; /* 0xc0 */
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A_UINT32 hi_console_flags; /* 0xc4 */
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A_UINT32 hi_nvram_state; /* 0xc8 */
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A_UINT32 hi_option_flag2; /* 0xcc */
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/* If non-zero, override values sent to Host in WMI_READY event. */
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A_UINT32 hi_sw_version_override; /* 0xd0 */
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A_UINT32 hi_abi_version_override; /* 0xd4 */
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/* Percentage of high priority RX traffic to total expected RX traffic -
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* applicable only to ar6004 */
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A_UINT32 hi_hp_rx_traffic_ratio; /* 0xd8 */
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/* test applications flags */
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A_UINT32 hi_test_apps_related; /* 0xdc */
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/* location of test script */
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A_UINT32 hi_ota_testscript; /* 0xe0 */
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/* location of CAL data */
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A_UINT32 hi_cal_data; /* 0xe4 */
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/* Number of packet log buffers */
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A_UINT32 hi_pktlog_num_buffers; /* 0xe8 */
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/* wow extension configuration */
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A_UINT32 hi_wow_ext_config; /* 0xec */
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A_UINT32 hi_pwr_save_flags; /* 0xf0 */
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/* Spatial Multiplexing Power Save (SMPS) options */
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A_UINT32 hi_smps_options; /* 0xf4 */
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/* Interconnect-specific state */
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A_UINT32 hi_interconnect_state; /* 0xf8 */
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/* Coex configuration flags */
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A_UINT32 hi_coex_config; /* 0xfc */
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/* Early allocation support */
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A_UINT32 hi_early_alloc; /* 0x100 */
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/* FW swap field */
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/* Bits of this 32bit word will be used to pass specific swap
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instruction to FW */
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/* Bit 0 -- AP Nart descriptor no swap. When this bit is set
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FW will not swap TX descriptor. Meaning packets are formed
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on the target processor. */
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/* Bit 1 -- TBD */
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A_UINT32 hi_fw_swap; /* 0x104 */
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/* global arenas pointer address, used by host driver debug */
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A_UINT32 hi_dynamic_mem_arenas_addr; /* 0x108 */
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/* allocated bytes of DRAM use by allocated */
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A_UINT32 hi_dynamic_mem_allocated; /* 0x10C */
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/* remaining bytes of DRAM */
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A_UINT32 hi_dynamic_mem_remaining; /* 0x110 */
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/* memory track count, configured by host */
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A_UINT32 hi_dynamic_mem_track_max; /* 0x114 */
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/* minidump buffer */
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A_UINT32 hi_minidump; /* 0x118 */
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/* bdata's sig and key addr */
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A_UINT32 hi_bd_sig_key; /* 0x11c */
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} POSTPACK64;
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/* bitmap for hi_test_apps_related */
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#define HI_TEST_APPS_TESTSCRIPT_LOADED 0x00000001
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#define HI_TEST_APPS_CAL_DATA_AVAIL 0x00000002
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/* Bits defined in hi_option_flag */
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#define HI_OPTION_TIMER_WAR 0x01 /* Enable timer workaround */
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#define HI_OPTION_BMI_CRED_LIMIT 0x02 /* Limit BMI command credits */
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#define HI_OPTION_RELAY_DOT11_HDR 0x04 /* Relay Dot11 hdr to/from host */
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#define HI_OPTION_MAC_ADDR_METHOD 0x08 /* MAC addr method 0-locally administred 1-globally unique addrs */
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#define HI_OPTION_FW_BRIDGE 0x10 /* Firmware Bridging */
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#define HI_OPTION_ENABLE_PROFILE 0x20 /* Enable CPU profiling */
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#define HI_OPTION_DISABLE_DBGLOG 0x40 /* Disable debug logging */
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#define HI_OPTION_SKIP_ERA_TRACKING 0x80 /* Skip Era Tracking */
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#define HI_OPTION_PAPRD_DISABLE 0x100 /* Disable PAPRD (debug) */
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#define HI_OPTION_NUM_DEV_LSB 0x200
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#define HI_OPTION_NUM_DEV_MSB 0x800
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#define HI_OPTION_DEV_MODE_LSB 0x1000
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#define HI_OPTION_DEV_MODE_MSB 0x8000000
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#define HI_OPTION_NO_LFT_STBL 0x10000000 /* Disable LowFreq Timer Stabilization */
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#define HI_OPTION_SKIP_REG_SCAN 0x20000000 /* Skip regulatory scan */
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#define HI_OPTION_INIT_REG_SCAN 0x40000000 /* Do regulatory scan during init before
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* sending WMI ready event to host */
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#define HI_OPTION_SKIP_MEMMAP 0x80000000 /* REV6: Do not adjust memory map */
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#define HI_OPTION_MAC_ADDR_METHOD_SHIFT 3
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/* 2 bits of hi_option_flag are used to represent 3 modes */
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#define HI_OPTION_FW_MODE_IBSS 0x0 /* IBSS Mode */
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#define HI_OPTION_FW_MODE_BSS_STA 0x1 /* STA Mode */
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#define HI_OPTION_FW_MODE_AP 0x2 /* AP Mode */
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#define HI_OPTION_FW_MODE_BT30AMP 0x3 /* BT30 AMP Mode */
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/* 2 bits of hi_option flag are usedto represent 4 submodes */
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#define HI_OPTION_FW_SUBMODE_NONE 0x0 /* Normal mode */
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#define HI_OPTION_FW_SUBMODE_P2PDEV 0x1 /* p2p device mode */
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#define HI_OPTION_FW_SUBMODE_P2PCLIENT 0x2 /* p2p client mode */
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#define HI_OPTION_FW_SUBMODE_P2PGO 0x3 /* p2p go mode */
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/* Num dev Mask */
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#define HI_OPTION_NUM_DEV_MASK 0x7
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#define HI_OPTION_NUM_DEV_SHIFT 0x9
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/* firmware bridging */
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#define HI_OPTION_FW_BRIDGE_SHIFT 0x04
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/* Fw Mode/SubMode Mask
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|-------------------------------------------------------------------------------|
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| SUB | SUB | SUB | SUB | | | | |
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| MODE[3] | MODE[2] | MODE[1] | MODE[0] | MODE[3] | MODE[2] | MODE[1] | MODE[0] |
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| (2) | (2) | (2) | (2) | (2) | (2) | (2) | (2) |
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|||-------------------------------------------------------------------------------|
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*/
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#define HI_OPTION_FW_MODE_BITS 0x2
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#define HI_OPTION_FW_MODE_MASK 0x3
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#define HI_OPTION_FW_MODE_SHIFT 0xC
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#define HI_OPTION_ALL_FW_MODE_MASK 0xFF
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#define HI_OPTION_FW_SUBMODE_BITS 0x2
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#define HI_OPTION_FW_SUBMODE_MASK 0x3
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#define HI_OPTION_FW_SUBMODE_SHIFT 0x14
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#define HI_OPTION_ALL_FW_SUBMODE_MASK 0xFF00
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#define HI_OPTION_ALL_FW_SUBMODE_SHIFT 0x8
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/* hi_option_flag2 options */
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#define HI_OPTION_OFFLOAD_AMSDU 0x01
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#define HI_OPTION_DFS_SUPPORT 0x02 /* Enable DFS support */
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#define HI_OPTION_ENABLE_RFKILL 0x04 /* RFKill Enable Feature */
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#define HI_OPTION_RADIO_RETENTION_DISABLE 0x08 /* Disable radio retention */
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#define HI_OPTION_EARLY_CFG_DONE 0x10 /* Early configuration is complete */
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#define HI_OPTION_RF_KILL_SHIFT 0x2
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#define HI_OPTION_RF_KILL_MASK 0x1
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/* AR9888 1.0 only. Enable/disable CDC max perf support from host */
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#define HI_OPTION_DISABLE_CDC_MAX_PERF_WAR 0x20
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#define CDC_MAX_PERF_WAR_ENABLED() \
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(!(HOST_INTEREST->hi_option_flag2 & HI_OPTION_DISABLE_CDC_MAX_PERF_WAR))
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#define HI_OPTION_USE_EXT_LDO 0x40 /* use LDO27 for 1.1V instead of PMU */
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#define HI_OPTION_DBUART_SUPPORT 0x80 /* Enable uart debug support */
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#define HT_OPTION_GPIO_WAKEUP_SUPPORT 0x200 /* GPIO wake up support */
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#define GPIO_WAKEUP_ENABLED() \
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(HOST_INTEREST->hi_option_flag2 & HT_OPTION_GPIO_WAKEUP_SUPPORT)
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/* hi_reset_flag */
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#define HI_RESET_FLAG_PRESERVE_APP_START 0x01 /* preserve App Start address */
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#define HI_RESET_FLAG_PRESERVE_HOST_INTEREST 0x02 /* preserve host interest */
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#define HI_RESET_FLAG_PRESERVE_ROMDATA 0x04 /* preserve ROM data */
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#define HI_RESET_FLAG_PRESERVE_NVRAM_STATE 0x08
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#define HI_RESET_FLAG_PRESERVE_BOOT_INFO 0x10
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#define HI_RESET_FLAG_WARM_RESET 0x20
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/* define hi_fw_swap bits */
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#define HI_DESC_IN_FW_BIT 0x01
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#define HI_RESET_FLAG_IS_VALID 0x12345678 /* indicate the reset flag is valid */
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#define ON_RESET_FLAGS_VALID() \
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(HOST_INTEREST->hi_reset_flag_valid == HI_RESET_FLAG_IS_VALID)
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#define RESET_FLAGS_VALIDATE() \
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(HOST_INTEREST->hi_reset_flag_valid = HI_RESET_FLAG_IS_VALID)
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#define RESET_FLAGS_INVALIDATE() \
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(HOST_INTEREST->hi_reset_flag_valid = 0)
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#define ON_RESET_PRESERVE_APP_START() \
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(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_APP_START)
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#define ON_RESET_PRESERVE_NVRAM_STATE() \
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(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_NVRAM_STATE)
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#define ON_RESET_PRESERVE_HOST_INTEREST() \
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(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_HOST_INTEREST)
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#define ON_RESET_PRESERVE_ROMDATA() \
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(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_ROMDATA)
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#define ON_RESET_PRESERVE_BOOT_INFO() \
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(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_PRESERVE_BOOT_INFO)
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#define ON_RESET_WARM_RESET() \
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(HOST_INTEREST->hi_reset_flag & HI_RESET_FLAG_WARM_RESET)
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/* host CPU endianness */
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#define HOST_ON_BE_CPU() \
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(HOST_INTEREST->hi_be)
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/* AP nart no swap descriptor flag. Decsriptors are created on the target processor. */
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#define DESC_IN_FW() \
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(HOST_INTEREST->hi_fw_swap & HI_DESC_IN_FW_BIT)
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#define HI_ACS_FLAGS_ENABLED (1 << 0) /* ACS is enabled */
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#define HI_ACS_FLAGS_USE_WWAN (1 << 1) /* Use physical WWAN device */
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#define HI_ACS_FLAGS_TEST_VAP (1 << 2) /* Use test VAP */
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/* CONSOLE FLAGS
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*
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* Bit Range Meaning
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* --------- --------------------------------
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* 2..0 UART ID (0 = Default)
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* 3 Baud Select (0 = 9600, 1 = 115200)
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* 30..4 Reserved
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* 31 Enable Console
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*
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* */
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#define HI_CONSOLE_FLAGS_ENABLE (1 << 31)
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#define HI_CONSOLE_FLAGS_UART_MASK (0x7)
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#define HI_CONSOLE_FLAGS_UART_SHIFT 0
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#define HI_CONSOLE_FLAGS_BAUD_SELECT (1 << 3)
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/* SM power save options */
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#define HI_SMPS_ALLOW_MASK (0x00000001)
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#define HI_SMPS_MODE_MASK (0x00000002)
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#define HI_SMPS_MODE_STATIC (0x00000000)
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#define HI_SMPS_MODE_DYNAMIC (0x00000002)
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#define HI_SMPS_DISABLE_AUTO_MODE (0x00000004)
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#define HI_SMPS_DATA_THRESH_MASK (0x000007f8)
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#define HI_SMPS_DATA_THRESH_SHIFT (3)
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#define HI_SMPS_RSSI_THRESH_MASK (0x0007f800)
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#define HI_SMPS_RSSI_THRESH_SHIFT (11)
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#define HI_SMPS_LOWPWR_CM_MASK (0x00380000)
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#define HI_SMPS_LOWPWR_CM_SHIFT (15)
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#define HI_SMPS_HIPWR_CM_MASK (0x03c00000)
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#define HI_SMPS_HIPWR_CM_SHIFT (19)
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#define HOST_INTEREST_SMPS_GET_MODE() (HOST_INTEREST->hi_smps_options & HI_SMPS_MODE_MASK)
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#define HOST_INTEREST_SMPS_GET_DATA_THRESH() ((HOST_INTEREST->hi_smps_options & HI_SMPS_DATA_THRESH_MASK) >> HI_SMPS_DATA_THRESH_SHIFT)
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#define HOST_INTEREST_SMPS_SET_DATA_THRESH(x) (((x) << HI_SMPS_DATA_THRESH_SHIFT) & HI_SMPS_DATA_THRESH_MASK)
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#define HOST_INTEREST_SMPS_GET_RSSI_THRESH() ((HOST_INTEREST->hi_smps_options & HI_SMPS_RSSI_THRESH_MASK) >> HI_SMPS_RSSI_THRESH_SHIFT)
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#define HOST_INTEREST_SMPS_SET_RSSI_THRESH(x) (((x) << HI_SMPS_RSSI_THRESH_SHIFT) & HI_SMPS_RSSI_THRESH_MASK)
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#define HOST_INTEREST_SMPS_SET_LOWPWR_CM() ((HOST_INTEREST->hi_smps_options & HI_SMPS_LOWPWR_CM_MASK) >> HI_SMPS_LOWPWR_CM_SHIFT)
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#define HOST_INTEREST_SMPS_SET_HIPWR_CM() ((HOST_INTEREST->hi_smps_options << HI_SMPS_HIPWR_CM_MASK) & HI_SMPS_HIPWR_CM_SHIFT)
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#define HOST_INTEREST_SMPS_IS_AUTO_MODE_DISABLED() (HOST_INTEREST->hi_smps_options & HI_SMPS_DISABLE_AUTO_MODE)
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/* WOW Extension configuration
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*
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* Bit Range Meaning
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* --------- --------------------------------
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* 8..0 Size of each WOW pattern (max 511)
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* 15..9 Number of patterns per list (max 127)
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* 17..16 Number of lists (max 4)
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* 30..18 Reserved
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* 31 Enabled
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*
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* set values (except enable) to zeros for default settings
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*
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* */
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#define HI_WOW_EXT_ENABLED_MASK (1 << 31)
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#define HI_WOW_EXT_NUM_LIST_SHIFT 16
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#define HI_WOW_EXT_NUM_LIST_MASK (0x3 << HI_WOW_EXT_NUM_LIST_SHIFT)
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#define HI_WOW_EXT_NUM_PATTERNS_SHIFT 9
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#define HI_WOW_EXT_NUM_PATTERNS_MASK (0x7F << HI_WOW_EXT_NUM_PATTERNS_SHIFT)
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#define HI_WOW_EXT_PATTERN_SIZE_SHIFT 0
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#define HI_WOW_EXT_PATTERN_SIZE_MASK (0x1FF << HI_WOW_EXT_PATTERN_SIZE_SHIFT)
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#define HI_WOW_EXT_MAKE_CONFIG(num_lists,count,size) \
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((((num_lists) << HI_WOW_EXT_NUM_LIST_SHIFT) & HI_WOW_EXT_NUM_LIST_MASK) | \
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(((count) << HI_WOW_EXT_NUM_PATTERNS_SHIFT) & HI_WOW_EXT_NUM_PATTERNS_MASK) | \
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(((size) << HI_WOW_EXT_PATTERN_SIZE_SHIFT) & HI_WOW_EXT_PATTERN_SIZE_MASK))
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#define HI_WOW_EXT_GET_NUM_LISTS(config) \
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(((config) & HI_WOW_EXT_NUM_LIST_MASK) >> HI_WOW_EXT_NUM_LIST_SHIFT)
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#define HI_WOW_EXT_GET_NUM_PATTERNS(config) \
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(((config) & HI_WOW_EXT_NUM_PATTERNS_MASK) >> HI_WOW_EXT_NUM_PATTERNS_SHIFT)
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#define HI_WOW_EXT_GET_PATTERN_SIZE(config) \
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(((config) & HI_WOW_EXT_PATTERN_SIZE_MASK) >> HI_WOW_EXT_PATTERN_SIZE_SHIFT)
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/*
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* Early allocation configuration
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* Support RAM bank configuration before BMI done and this eases the memory
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* allocation at very early stage
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* Bit Range Meaning
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* --------- ----------------------------------
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* [0:3] number of bank assigned to be IRAM
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* [4:15] reserved
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* [16:31] magic number
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*
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* Note:
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* 1. target firmware would check magic number and if it's a match, firmware
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* would consider the bits[0:15] are valid and base on that to calculate
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* the end of DRAM. Early allocation would be located at that area and
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* may be reclaimed when necesary
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* 2. if no magic number is found, early allocation would happen at "_end"
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|
* symbol of ROM which is located before the app-data and might NOT be
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* re-claimable. If this is adopted, link script should keep this in
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* mind to avoid data corruption.
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*/
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#define HI_EARLY_ALLOC_MAGIC 0x6d8a
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#define HI_EARLY_ALLOC_MAGIC_MASK 0xffff0000
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#define HI_EARLY_ALLOC_MAGIC_SHIFT 16
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#define HI_EARLY_ALLOC_IRAM_BANKS_MASK 0x0000000f
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#define HI_EARLY_ALLOC_IRAM_BANKS_SHIFT 0
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#define HI_EARLY_ALLOC_VALID() \
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((((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_MAGIC_MASK) >> HI_EARLY_ALLOC_MAGIC_SHIFT) \
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== (HI_EARLY_ALLOC_MAGIC))
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#define HI_EARLY_ALLOC_GET_IRAM_BANKS() \
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(((HOST_INTEREST->hi_early_alloc) & HI_EARLY_ALLOC_IRAM_BANKS_MASK) >> HI_EARLY_ALLOC_IRAM_BANKS_SHIFT)
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/*
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* Intended for use by Host software, this macro returns the Target RAM
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* address of any item in the host_interest structure.
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* Example: target_addr = AR6002_HOST_INTEREST_ITEM_ADDRESS(hi_board_data);
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*/
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#define AR6002_HOST_INTEREST_ITEM_ADDRESS(item) \
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(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6002_HOST_INTEREST_ADDRESS))->item)))
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#define AR6003_HOST_INTEREST_ITEM_ADDRESS(item) \
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(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6003_HOST_INTEREST_ADDRESS))->item)))
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#define AR6004_HOST_INTEREST_ITEM_ADDRESS(item) \
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(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6004_HOST_INTEREST_ADDRESS))->item)))
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#define AR6006_HOST_INTEREST_ITEM_ADDRESS(item) \
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(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6006_HOST_INTEREST_ADDRESS))->item)))
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#define AR9888_HOST_INTEREST_ITEM_ADDRESS(item) \
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(A_UINT32)((size_t)&((((struct host_interest_s *)(AR9888_HOST_INTEREST_ADDRESS))->item)))
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#define AR6320_HOST_INTEREST_ITEM_ADDRESS(item) \
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(A_UINT32)((size_t)&((((struct host_interest_s *)(AR6320_HOST_INTEREST_ADDRESS))->item)))
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#define AR900B_HOST_INTEREST_ITEM_ADDRESS(item) \
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(A_UINT32)((size_t)&((((struct host_interest_s *)(AR900B_HOST_INTEREST_ADDRESS))->item)))
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#define HOST_INTEREST_DBGLOG_IS_ENABLED() \
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(!((volatile A_UINT32)HOST_INTEREST->hi_option_flag & HI_OPTION_DISABLE_DBGLOG))
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#define HOST_INTEREST_PKTLOG_IS_ENABLED() \
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(((volatile A_UINT32)HOST_INTEREST->hi_pktlog_num_buffers))
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#define HOST_INTEREST_PROFILE_IS_ENABLED() \
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((volatile A_UINT32)HOST_INTEREST->hi_option_flag & HI_OPTION_ENABLE_PROFILE)
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#define LF_TIMER_STABILIZATION_IS_ENABLED() \
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(!((volatile A_UINT32)HOST_INTEREST->hi_option_flag & HI_OPTION_NO_LFT_STBL))
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#define IS_AMSDU_OFFLAOD_ENABLED() \
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(((volatile A_UINT32)HOST_INTEREST->hi_option_flag2 & HI_OPTION_OFFLOAD_AMSDU))
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#define HOST_INTEREST_DFS_IS_ENABLED() \
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(((volatile A_UINT32)HOST_INTEREST->hi_option_flag2 & HI_OPTION_DFS_SUPPORT))
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#define HOST_INTEREST_EARLY_CFG_DONE() \
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(((volatile A_UINT32)HOST_INTEREST->hi_option_flag2 & HI_OPTION_EARLY_CFG_DONE))
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/*power save flag bit definitions*/
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#define HI_PWR_SAVE_LPL_ENABLED 0x1
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|
/*b1-b3 reserved*/
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|
/*b4-b5 : dev0 LPL type : 0 - none
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|
1- Reduce Pwr Search
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|
2- Reduce Pwr Listen*/
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|
/*b6-b7 : dev1 LPL type and so on for Max 8 devices*/
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|
#define HI_PWR_SAVE_LPL_DEV0_LSB 4
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#define HI_PWR_SAVE_LPL_DEV_MASK 0x3
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|
/*power save related utility macros*/
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|
#define HI_LPL_ENABLED() \
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|
((HOST_INTEREST->hi_pwr_save_flags & HI_PWR_SAVE_LPL_ENABLED))
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|
#define HI_DEV_LPL_TYPE_GET(_devix) \
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|
(HOST_INTEREST->hi_pwr_save_flags & \
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|
((HI_PWR_SAVE_LPL_DEV_MASK) << \
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|
(HI_PWR_SAVE_LPL_DEV0_LSB + \
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|
(_devix)*2)))
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|
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|
#define HOST_INTEREST_SMPS_IS_ALLOWED() \
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|
((HOST_INTEREST->hi_smps_options & HI_SMPS_ALLOW_MASK))
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|
|
/* Convert a Target virtual address into a Target physical address */
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|
#define AR6002_VTOP(vaddr) ((vaddr) & 0x001fffff)
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|
#define AR6003_VTOP(vaddr) ((vaddr) & 0x001fffff)
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|
#define AR6004_VTOP(vaddr) (vaddr)
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|
#define AR6006_VTOP(vaddr) (vaddr)
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|
#define AR9888_VTOP(vaddr) (vaddr)
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|
#define AR6320_VTOP(vaddr) (vaddr)
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|
#define AR900B_VTOP(vaddr) (vaddr)
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|
#define TARG_VTOP(TargetType, vaddr) \
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|
(((TargetType) == TARGET_TYPE_AR6002) ? AR6002_VTOP(vaddr) : \
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|
(((TargetType) == TARGET_TYPE_AR6003) ? AR6003_VTOP(vaddr) : \
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|
(((TargetType) == TARGET_TYPE_AR6004) ? AR6004_VTOP(vaddr) : \
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|
(((TargetType) == TARGET_TYPE_AR6006) ? AR6006_VTOP(vaddr) : \
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|
(((TargetType) == TARGET_TYPE_AR9888) ? AR9888_VTOP(vaddr) : \
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|
(((TargetType) == TARGET_TYPE_AR6320) ? AR6320_VTOP(vaddr) : \
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|
(((TargetType) == TARGET_TYPE_AR900B) ? AR900B_VTOP(vaddr) : \
|
|
0)))))))
|
|
|
|
#define HOST_INTEREST_ITEM_ADDRESS(TargetType, item) \
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|
(((TargetType) == TARGET_TYPE_AR6002) ? AR6002_HOST_INTEREST_ITEM_ADDRESS(item) : \
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|
(((TargetType) == TARGET_TYPE_AR6003) ? AR6003_HOST_INTEREST_ITEM_ADDRESS(item) : \
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|
(((TargetType) == TARGET_TYPE_AR6004) ? AR6004_HOST_INTEREST_ITEM_ADDRESS(item) : \
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|
(((TargetType) == TARGET_TYPE_AR6006) ? AR6006_HOST_INTEREST_ITEM_ADDRESS(item) : \
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|
(((TargetType) == TARGET_TYPE_AR9888) ? AR9888_HOST_INTEREST_ITEM_ADDRESS(item) : \
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|
(((TargetType) == TARGET_TYPE_AR6320) ? AR6320_HOST_INTEREST_ITEM_ADDRESS(item) : \
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|
(((TargetType) == TARGET_TYPE_AR6320V2) ? AR6320_HOST_INTEREST_ITEM_ADDRESS(item) : \
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|
(((TargetType) == TARGET_TYPE_AR900B) ? AR900B_HOST_INTEREST_ITEM_ADDRESS(item) : \
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|
0))))))))
|
|
|
|
#define AR6002_BOARD_DATA_SZ 768
|
|
#define AR6002_BOARD_EXT_DATA_SZ 0
|
|
#define AR6003_BOARD_DATA_SZ 1024
|
|
/* Reserve 1024 bytes for extended board data */
|
|
#if defined(AR6002_REV43)
|
|
#define AR6003_BOARD_EXT_DATA_SZ 1024
|
|
#else
|
|
#define AR6003_BOARD_EXT_DATA_SZ 768
|
|
#endif
|
|
#define AR6004_BOARD_DATA_SZ 7168
|
|
#define AR6004_BOARD_EXT_DATA_SZ 0
|
|
#define AR9888_BOARD_DATA_SZ 7168
|
|
#define AR9888_BOARD_EXT_DATA_SZ 0
|
|
#define AR6320_BOARD_DATA_SZ 8192
|
|
#define AR6320_BOARD_EXT_DATA_SZ 0
|
|
#define AR900B_BOARD_DATA_SZ 7168
|
|
#define AR900B_BOARD_EXT_DATA_SZ 0
|
|
|
|
#define AR6003_REV3_APP_START_OVERRIDE 0x946100
|
|
#define AR6003_REV3_APP_LOAD_ADDRESS 0x545000
|
|
#define AR6003_REV3_BOARD_EXT_DATA_ADDRESS 0x542330
|
|
#define AR6003_REV3_DATASET_PATCH_ADDRESS 0x57FF74
|
|
#define AR6003_REV3_RAM_RESERVE_SIZE 4096
|
|
|
|
#define AR6004_REV1_BOARD_DATA_ADDRESS 0x423900
|
|
#define AR6004_REV1_RAM_RESERVE_SIZE 19456
|
|
#define AR6004_REV1_DATASET_PATCH_ADDRESS 0x425294
|
|
|
|
#define AR6004_REV2_BOARD_DATA_ADDRESS 0x426400
|
|
#define AR6004_REV2_RAM_RESERVE_SIZE 7168
|
|
#define AR6004_REV2_DATASET_PATCH_ADDRESS 0x435294
|
|
|
|
#define AR6004_REV5_BOARD_DATA_ADDRESS 0x436400
|
|
#define AR6004_REV5_RAM_RESERVE_SIZE 7168
|
|
#define AR6004_REV5_DATASET_PATCH_ADDRESS 0x437860
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|
|
|
/* Reserve 4K for OTA test script */
|
|
#define AR6004_REV1_RAM_RESERVE_SIZE_FOR_TEST_SCRIPT 4096
|
|
#define AR6004_REV1_TEST_SCRIPT_ADDRESS 0x422900
|
|
|
|
/* # of A_UINT32 entries in targregs, used by DIAG_FETCH_TARG_REGS */
|
|
#define AR6003_FETCH_TARG_REGS_COUNT 64
|
|
#define AR6004_FETCH_TARG_REGS_COUNT 64
|
|
#define AR9888_FETCH_TARG_REGS_COUNT 64
|
|
#define AR6320_FETCH_TARG_REGS_COUNT 64
|
|
#define AR900B_FETCH_TARG_REGS_COUNT 64
|
|
|
|
#endif /* !__ASSEMBLER__ */
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|
|
#ifndef ATH_TARGET
|
|
#include "athendpack.h"
|
|
#endif
|
|
|
|
#endif /* __TARGADDRS_H__ */
|