3f2d560e90
This patch has reworked cobalt_board_id. The cobalt_board_id is read from PCI config register. It should be in PCI routine. Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
147 lines
3.4 KiB
C
147 lines
3.4 KiB
C
/*
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* Setup pointers to hardware dependent routines.
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*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1996, 1997, 2004, 05 by Ralf Baechle (ralf@linux-mips.org)
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* Copyright (C) 2001, 2002, 2003 by Liam Davies (ldavies@agile.tv)
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*
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*/
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#include <linux/interrupt.h>
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#include <linux/init.h>
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#include <linux/pm.h>
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#include <asm/bootinfo.h>
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#include <asm/time.h>
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#include <asm/io.h>
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#include <asm/reboot.h>
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#include <asm/gt64120.h>
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#include <cobalt.h>
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extern void cobalt_machine_restart(char *command);
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extern void cobalt_machine_halt(void);
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extern void cobalt_machine_power_off(void);
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const char *get_system_type(void)
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{
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switch (cobalt_board_id) {
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case COBALT_BRD_ID_QUBE1:
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return "Cobalt Qube";
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case COBALT_BRD_ID_RAQ1:
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return "Cobalt RaQ";
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case COBALT_BRD_ID_QUBE2:
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return "Cobalt Qube2";
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case COBALT_BRD_ID_RAQ2:
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return "Cobalt RaQ2";
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}
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return "MIPS Cobalt";
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}
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void __init plat_timer_setup(struct irqaction *irq)
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{
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/* Load timer value for HZ (TCLK is 50MHz) */
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GT_WRITE(GT_TC0_OFS, 50*1000*1000 / HZ);
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/* Enable timer */
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GT_WRITE(GT_TC_CONTROL_OFS, GT_TC_CONTROL_ENTC0_MSK | GT_TC_CONTROL_SELTC0_MSK);
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/* Register interrupt */
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setup_irq(COBALT_GALILEO_IRQ, irq);
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/* Enable interrupt */
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GT_WRITE(GT_INTRMASK_OFS, GT_INTR_T0EXP_MSK | GT_READ(GT_INTRMASK_OFS));
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}
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/*
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* Cobalt doesn't have PS/2 keyboard/mouse interfaces,
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* keyboard conntroller is never used.
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* Also PCI-ISA bridge DMA contoroller is never used.
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*/
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static struct resource cobalt_reserved_resources[] = {
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{ /* dma1 */
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.start = 0x00,
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.end = 0x1f,
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.name = "reserved",
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.flags = IORESOURCE_BUSY | IORESOURCE_IO,
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},
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{ /* keyboard */
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.start = 0x60,
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.end = 0x6f,
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.name = "reserved",
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.flags = IORESOURCE_BUSY | IORESOURCE_IO,
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},
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{ /* dma page reg */
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.start = 0x80,
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.end = 0x8f,
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.name = "reserved",
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.flags = IORESOURCE_BUSY | IORESOURCE_IO,
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},
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{ /* dma2 */
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.start = 0xc0,
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.end = 0xdf,
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.name = "reserved",
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.flags = IORESOURCE_BUSY | IORESOURCE_IO,
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},
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};
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void __init plat_mem_setup(void)
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{
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int i;
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_machine_restart = cobalt_machine_restart;
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_machine_halt = cobalt_machine_halt;
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pm_power_off = cobalt_machine_power_off;
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set_io_port_base(CKSEG1ADDR(GT_DEF_PCI0_IO_BASE));
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/* I/O port resource must include LCD/buttons */
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ioport_resource.end = 0x0fffffff;
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/* These resources have been reserved by VIA SuperI/O chip. */
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for (i = 0; i < ARRAY_SIZE(cobalt_reserved_resources); i++)
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request_resource(&ioport_resource, cobalt_reserved_resources + i);
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}
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/*
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* Prom init. We read our one and only communication with the firmware.
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* Grab the amount of installed memory.
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* Better boot loaders (CoLo) pass a command line too :-)
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*/
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void __init prom_init(void)
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{
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int narg, indx, posn, nchr;
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unsigned long memsz;
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char **argv;
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mips_machgroup = MACH_GROUP_COBALT;
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memsz = fw_arg0 & 0x7fff0000;
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narg = fw_arg0 & 0x0000ffff;
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if (narg) {
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arcs_cmdline[0] = '\0';
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argv = (char **) fw_arg1;
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posn = 0;
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for (indx = 1; indx < narg; ++indx) {
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nchr = strlen(argv[indx]);
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if (posn + 1 + nchr + 1 > sizeof(arcs_cmdline))
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break;
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if (posn)
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arcs_cmdline[posn++] = ' ';
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strcpy(arcs_cmdline + posn, argv[indx]);
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posn += nchr;
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}
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}
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add_memory_region(0x0, memsz, BOOT_MEM_RAM);
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}
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void __init prom_free_prom_memory(void)
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{
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/* Nothing to do! */
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}
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