7c2a6c62c0
The Altix subarch does not provide node information via ACPI. Instead hooks are used to fixup pci structures. This patch determines the nodes for Altix PCI busses. Remote Bridges: --------------- Altix supports remote I/O nodes without memory or processors but with bridges. The TIOCA type of bridge is an AGP bridge and the PROM provides information about the closest node. That information will be returned by pcibus_to_node. The TIOCP remote bridge type is a PCI bridge but the PROM does not provide a closest node id. pcibus_to_node will return -1 for devices on those bridges meaning that device control structures may be allocated on any node. Safeguard: ---------- Should the fixups result in invalid node information for a pci controller then a warning will be printed and pcibus_to_node will return -1. This patch also fixes the "FIXME" in sn_dma_alloc_coherent. This means that dma_alloc_coherent will now use alloc_pages_node to allocate memory local to the node that the PCI device is connected to. Signed-off-by: Christoph Lameter <clameter@sgi.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
54 lines
1.6 KiB
C
54 lines
1.6 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1992 - 1997, 2000-2004 Silicon Graphics, Inc. All rights reserved.
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*/
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#ifndef _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H
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#define _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H
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/*
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* SN pci asic types. Do not ever renumber these or reuse values. The
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* values must agree with what prom thinks they are.
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*/
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#define PCIIO_ASIC_TYPE_UNKNOWN 0
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#define PCIIO_ASIC_TYPE_PPB 1
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#define PCIIO_ASIC_TYPE_PIC 2
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#define PCIIO_ASIC_TYPE_TIOCP 3
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#define PCIIO_ASIC_TYPE_TIOCA 4
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#define PCIIO_ASIC_MAX_TYPES 5
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/*
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* Common pciio bus provider data. There should be one of these as the
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* first field in any pciio based provider soft structure (e.g. pcibr_soft
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* tioca_soft, etc).
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*/
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struct pcibus_bussoft {
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uint32_t bs_asic_type; /* chipset type */
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uint32_t bs_xid; /* xwidget id */
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uint64_t bs_persist_busnum; /* Persistent Bus Number */
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uint64_t bs_legacy_io; /* legacy io pio addr */
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uint64_t bs_legacy_mem; /* legacy mem pio addr */
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uint64_t bs_base; /* widget base */
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struct xwidget_info *bs_xwidget_info;
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};
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struct pci_controller;
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/*
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* SN pci bus indirection
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*/
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struct sn_pcibus_provider {
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dma_addr_t (*dma_map)(struct pci_dev *, unsigned long, size_t);
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dma_addr_t (*dma_map_consistent)(struct pci_dev *, unsigned long, size_t);
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void (*dma_unmap)(struct pci_dev *, dma_addr_t, int);
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void * (*bus_fixup)(struct pcibus_bussoft *, struct pci_controller *);
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};
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extern struct sn_pcibus_provider *sn_pci_provider[];
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#endif /* _ASM_IA64_SN_PCI_PCIBUS_PROVIDER_H */
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