3c42a44910
Signed-off-by: Daniel Mack <daniel@caiaq.de> Signed-off-by: Eric Miao <eric.miao@marvell.com> Cc: "Antonino A. Daplas" <adaplas@pol.net> Cc: Russell King <rmk@arm.linux.org.uk> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
172 lines
7.7 KiB
C
172 lines
7.7 KiB
C
#ifndef __ASM_ARCH_REGS_LCD_H
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#define __ASM_ARCH_REGS_LCD_H
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/*
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* LCD Controller Registers and Bits Definitions
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*/
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#define LCCR0 (0x000) /* LCD Controller Control Register 0 */
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#define LCCR1 (0x004) /* LCD Controller Control Register 1 */
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#define LCCR2 (0x008) /* LCD Controller Control Register 2 */
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#define LCCR3 (0x00C) /* LCD Controller Control Register 3 */
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#define LCCR4 (0x010) /* LCD Controller Control Register 4 */
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#define LCCR5 (0x014) /* LCD Controller Control Register 5 */
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#define DFBR0 (0x020) /* DMA Channel 0 Frame Branch Register */
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#define DFBR1 (0x024) /* DMA Channel 1 Frame Branch Register */
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#define LCSR (0x038) /* LCD Controller Status Register */
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#define LIIDR (0x03C) /* LCD Controller Interrupt ID Register */
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#define TMEDRGBR (0x040) /* TMED RGB Seed Register */
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#define TMEDCR (0x044) /* TMED Control Register */
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#define CMDCR (0x100) /* Command Control Register */
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#define PRSR (0x104) /* Panel Read Status Register */
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#define LCCR3_1BPP (0 << 24)
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#define LCCR3_2BPP (1 << 24)
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#define LCCR3_4BPP (2 << 24)
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#define LCCR3_8BPP (3 << 24)
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#define LCCR3_16BPP (4 << 24)
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#define LCCR3_PDFOR_0 (0 << 30)
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#define LCCR3_PDFOR_1 (1 << 30)
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#define LCCR3_PDFOR_2 (2 << 30)
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#define LCCR3_PDFOR_3 (3 << 30)
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#define LCCR4_PAL_FOR_0 (0 << 15)
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#define LCCR4_PAL_FOR_1 (1 << 15)
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#define LCCR4_PAL_FOR_2 (2 << 15)
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#define LCCR4_PAL_FOR_MASK (3 << 15)
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#define FDADR0 (0x200) /* DMA Channel 0 Frame Descriptor Address Register */
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#define FSADR0 (0x204) /* DMA Channel 0 Frame Source Address Register */
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#define FIDR0 (0x208) /* DMA Channel 0 Frame ID Register */
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#define LDCMD0 (0x20C) /* DMA Channel 0 Command Register */
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#define FDADR1 (0x210) /* DMA Channel 1 Frame Descriptor Address Register */
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#define FSADR1 (0x214) /* DMA Channel 1 Frame Source Address Register */
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#define FIDR1 (0x218) /* DMA Channel 1 Frame ID Register */
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#define LDCMD1 (0x21C) /* DMA Channel 1 Command Register */
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#define FDADR6 (0x260) /* DMA Channel 6 Frame Descriptor Address Register */
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#define FSADR6 (0x264) /* DMA Channel 6 Frame Source Address Register */
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#define FIDR6 (0x268) /* DMA Channel 6 Frame ID Register */
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#define LCCR0_ENB (1 << 0) /* LCD Controller enable */
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#define LCCR0_CMS (1 << 1) /* Color/Monochrome Display Select */
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#define LCCR0_Color (LCCR0_CMS*0) /* Color display */
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#define LCCR0_Mono (LCCR0_CMS*1) /* Monochrome display */
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#define LCCR0_SDS (1 << 2) /* Single/Dual Panel Display Select */
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#define LCCR0_Sngl (LCCR0_SDS*0) /* Single panel display */
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#define LCCR0_Dual (LCCR0_SDS*1) /* Dual panel display */
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#define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */
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#define LCCR0_SFM (1 << 4) /* Start of frame mask */
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#define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */
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#define LCCR0_EFM (1 << 6) /* End of Frame mask */
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#define LCCR0_PAS (1 << 7) /* Passive/Active display Select */
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#define LCCR0_Pas (LCCR0_PAS*0) /* Passive display (STN) */
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#define LCCR0_Act (LCCR0_PAS*1) /* Active display (TFT) */
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#define LCCR0_DPD (1 << 9) /* Double Pixel Data (monochrome) */
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#define LCCR0_4PixMono (LCCR0_DPD*0) /* 4-Pixel/clock Monochrome display */
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#define LCCR0_8PixMono (LCCR0_DPD*1) /* 8-Pixel/clock Monochrome display */
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#define LCCR0_DIS (1 << 10) /* LCD Disable */
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#define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */
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#define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */
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#define LCCR0_PDD_S 12
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#define LCCR0_BM (1 << 20) /* Branch mask */
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#define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */
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#define LCCR0_LCDT (1 << 22) /* LCD panel type */
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#define LCCR0_RDSTM (1 << 23) /* Read status interrupt mask */
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#define LCCR0_CMDIM (1 << 24) /* Command interrupt mask */
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#define LCCR0_OUC (1 << 25) /* Overlay Underlay control bit */
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#define LCCR0_LDDALT (1 << 26) /* LDD alternate mapping control */
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#define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
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#define LCCR1_DisWdth(Pixel) (((Pixel) - 1) << FShft (LCCR1_PPL))
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#define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */
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#define LCCR1_HorSnchWdth(Tpix) (((Tpix) - 1) << FShft (LCCR1_HSW))
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#define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait - 1 */
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#define LCCR1_EndLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_ELW))
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#define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
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#define LCCR1_BegLnDel(Tpix) (((Tpix) - 1) << FShft (LCCR1_BLW))
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#define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
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#define LCCR2_DisHght(Line) (((Line) - 1) << FShft (LCCR2_LPP))
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#define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse - 1 */
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#define LCCR2_VrtSnchWdth(Tln) (((Tln) - 1) << FShft (LCCR2_VSW))
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#define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
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#define LCCR2_EndFrmDel(Tln) ((Tln) << FShft (LCCR2_EFW))
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#define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
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#define LCCR2_BegFrmDel(Tln) ((Tln) << FShft (LCCR2_BFW))
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#define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */
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#define LCCR3_API_S 16
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#define LCCR3_VSP (1 << 20) /* vertical sync polarity */
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#define LCCR3_HSP (1 << 21) /* horizontal sync polarity */
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#define LCCR3_PCP (1 << 22) /* Pixel Clock Polarity (L_PCLK) */
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#define LCCR3_PixRsEdg (LCCR3_PCP*0) /* Pixel clock Rising-Edge */
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#define LCCR3_PixFlEdg (LCCR3_PCP*1) /* Pixel clock Falling-Edge */
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#define LCCR3_OEP (1 << 23) /* Output Enable Polarity */
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#define LCCR3_OutEnH (LCCR3_OEP*0) /* Output Enable active High */
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#define LCCR3_OutEnL (LCCR3_OEP*1) /* Output Enable active Low */
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#define LCCR3_DPC (1 << 27) /* double pixel clock mode */
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#define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */
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#define LCCR3_PixClkDiv(Div) (((Div) << FShft (LCCR3_PCD)))
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#define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */
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#define LCCR3_Bpp(Bpp) (((Bpp) << FShft (LCCR3_BPP)))
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#define LCCR3_ACB Fld (8, 8) /* AC Bias */
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#define LCCR3_Acb(Acb) (((Acb) << FShft (LCCR3_ACB)))
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#define LCCR3_HorSnchH (LCCR3_HSP*0) /* HSP Active High */
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#define LCCR3_HorSnchL (LCCR3_HSP*1) /* HSP Active Low */
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#define LCCR3_VrtSnchH (LCCR3_VSP*0) /* VSP Active High */
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#define LCCR3_VrtSnchL (LCCR3_VSP*1) /* VSP Active Low */
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#define LCCR5_IUM(x) (1 << ((x) + 23)) /* input underrun mask */
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#define LCCR5_BSM(x) (1 << ((x) + 15)) /* branch mask */
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#define LCCR5_EOFM(x) (1 << ((x) + 7)) /* end of frame mask */
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#define LCCR5_SOFM(x) (1 << ((x) + 0)) /* start of frame mask */
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#define LCSR_LDD (1 << 0) /* LCD Disable Done */
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#define LCSR_SOF (1 << 1) /* Start of frame */
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#define LCSR_BER (1 << 2) /* Bus error */
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#define LCSR_ABC (1 << 3) /* AC Bias count */
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#define LCSR_IUL (1 << 4) /* input FIFO underrun Lower panel */
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#define LCSR_IUU (1 << 5) /* input FIFO underrun Upper panel */
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#define LCSR_OU (1 << 6) /* output FIFO underrun */
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#define LCSR_QD (1 << 7) /* quick disable */
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#define LCSR_EOF (1 << 8) /* end of frame */
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#define LCSR_BS (1 << 9) /* branch status */
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#define LCSR_SINT (1 << 10) /* subsequent interrupt */
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#define LCSR_RD_ST (1 << 11) /* read status */
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#define LCSR_CMD_INT (1 << 12) /* command interrupt */
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#define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
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/* smartpanel related */
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#define PRSR_DATA(x) ((x) & 0xff) /* Panel Data */
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#define PRSR_A0 (1 << 8) /* Read Data Source */
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#define PRSR_ST_OK (1 << 9) /* Status OK */
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#define PRSR_CON_NT (1 << 10) /* Continue to Next Command */
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#define SMART_CMD_A0 (0x1 << 8)
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#define SMART_CMD_READ_STATUS_REG (0x0 << 9)
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#define SMART_CMD_READ_FRAME_BUFFER ((0x0 << 9) | SMART_CMD_A0)
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#define SMART_CMD_WRITE_COMMAND (0x1 << 9)
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#define SMART_CMD_WRITE_DATA ((0x1 << 9) | SMART_CMD_A0)
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#define SMART_CMD_WRITE_FRAME ((0x2 << 9) | SMART_CMD_A0)
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#define SMART_CMD_WAIT_FOR_VSYNC (0x3 << 9)
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#define SMART_CMD_NOOP (0x4 << 9)
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#define SMART_CMD_INTERRUPT (0x5 << 9)
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#define SMART_CMD(x) (SMART_CMD_WRITE_COMMAND | ((x) & 0xff))
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#define SMART_DAT(x) (SMART_CMD_WRITE_DATA | ((x) & 0xff))
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#endif /* __ASM_ARCH_REGS_LCD_H */
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