accf5ef254
This patch adds runtime detection of the 440SPe revision A chips. These
chips are equipped with a slighly different PCIe core and need special/
different initialization. The compatible node is changed to
"plb-pciex-440spe" ("A" and "B" dropped). This is needed for boards that
can be equipped with both PPC revisions like the AMCC Yucca.
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
393 lines
11 KiB
Plaintext
393 lines
11 KiB
Plaintext
/*
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* Device Tree Source for AMCC Katmai eval board
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*
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* Copyright (c) 2006, 2007 IBM Corp.
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* Benjamin Herrenschmidt <benh@kernel.crashing.org>
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*
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* Copyright (c) 2006, 2007 IBM Corp.
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* Josh Boyer <jwboyer@linux.vnet.ibm.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without
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* any warranty of any kind, whether express or implied.
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*/
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/ {
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#address-cells = <2>;
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#size-cells = <1>;
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model = "amcc,katmai";
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compatible = "amcc,katmai";
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dcr-parent = <&/cpus/PowerPC,440SPe@0>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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PowerPC,440SPe@0 {
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device_type = "cpu";
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reg = <0>;
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clock-frequency = <0>; /* Filled in by zImage */
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timebase-frequency = <0>; /* Filled in by zImage */
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i-cache-line-size = <20>;
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d-cache-line-size = <20>;
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i-cache-size = <20000>;
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d-cache-size = <20000>;
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dcr-controller;
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dcr-access-method = "native";
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};
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};
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memory {
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device_type = "memory";
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reg = <0 0 0>; /* Filled in by zImage */
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};
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UIC0: interrupt-controller0 {
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compatible = "ibm,uic-440spe","ibm,uic";
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interrupt-controller;
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cell-index = <0>;
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dcr-reg = <0c0 009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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};
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UIC1: interrupt-controller1 {
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compatible = "ibm,uic-440spe","ibm,uic";
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interrupt-controller;
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cell-index = <1>;
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dcr-reg = <0d0 009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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interrupts = <1e 4 1f 4>; /* cascade */
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interrupt-parent = <&UIC0>;
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};
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UIC2: interrupt-controller2 {
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compatible = "ibm,uic-440spe","ibm,uic";
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interrupt-controller;
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cell-index = <2>;
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dcr-reg = <0e0 009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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interrupts = <a 4 b 4>; /* cascade */
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interrupt-parent = <&UIC0>;
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};
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UIC3: interrupt-controller3 {
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compatible = "ibm,uic-440spe","ibm,uic";
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interrupt-controller;
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cell-index = <3>;
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dcr-reg = <0f0 009>;
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#address-cells = <0>;
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#size-cells = <0>;
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#interrupt-cells = <2>;
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interrupts = <10 4 11 4>; /* cascade */
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interrupt-parent = <&UIC0>;
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};
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SDR0: sdr {
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compatible = "ibm,sdr-440spe";
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dcr-reg = <00e 002>;
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};
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CPR0: cpr {
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compatible = "ibm,cpr-440spe";
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dcr-reg = <00c 002>;
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};
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plb {
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compatible = "ibm,plb-440spe", "ibm,plb-440gp", "ibm,plb4";
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#address-cells = <2>;
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#size-cells = <1>;
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ranges;
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clock-frequency = <0>; /* Filled in by zImage */
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SDRAM0: sdram {
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compatible = "ibm,sdram-440spe", "ibm,sdram-405gp";
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dcr-reg = <010 2>;
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};
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MAL0: mcmal {
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compatible = "ibm,mcmal-440spe", "ibm,mcmal2";
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dcr-reg = <180 62>;
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num-tx-chans = <2>;
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num-rx-chans = <1>;
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interrupt-parent = <&MAL0>;
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interrupts = <0 1 2 3 4>;
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#interrupt-cells = <1>;
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#address-cells = <0>;
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#size-cells = <0>;
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interrupt-map = </*TXEOB*/ 0 &UIC1 6 4
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/*RXEOB*/ 1 &UIC1 7 4
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/*SERR*/ 2 &UIC1 1 4
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/*TXDE*/ 3 &UIC1 2 4
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/*RXDE*/ 4 &UIC1 3 4>;
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};
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POB0: opb {
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compatible = "ibm,opb-440spe", "ibm,opb-440gp", "ibm,opb";
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <00000000 4 e0000000 20000000>;
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clock-frequency = <0>; /* Filled in by zImage */
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EBC0: ebc {
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compatible = "ibm,ebc-440spe", "ibm,ebc-440gp", "ibm,ebc";
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dcr-reg = <012 2>;
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#address-cells = <2>;
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#size-cells = <1>;
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clock-frequency = <0>; /* Filled in by zImage */
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interrupts = <5 1>;
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interrupt-parent = <&UIC1>;
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};
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UART0: serial@10000200 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <10000200 8>;
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virtual-reg = <a0000200>;
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clock-frequency = <0>; /* Filled in by zImage */
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current-speed = <1c200>;
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interrupt-parent = <&UIC0>;
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interrupts = <0 4>;
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};
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UART1: serial@10000300 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <10000300 8>;
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virtual-reg = <a0000300>;
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clock-frequency = <0>;
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current-speed = <0>;
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interrupt-parent = <&UIC0>;
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interrupts = <1 4>;
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};
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UART2: serial@10000600 {
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device_type = "serial";
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compatible = "ns16550";
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reg = <10000600 8>;
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virtual-reg = <a0000600>;
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clock-frequency = <0>;
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current-speed = <0>;
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interrupt-parent = <&UIC1>;
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interrupts = <5 4>;
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};
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IIC0: i2c@10000400 {
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device_type = "i2c";
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compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
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reg = <10000400 14>;
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interrupt-parent = <&UIC0>;
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interrupts = <2 4>;
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};
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IIC1: i2c@10000500 {
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device_type = "i2c";
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compatible = "ibm,iic-440spe", "ibm,iic-440gp", "ibm,iic";
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reg = <10000500 14>;
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interrupt-parent = <&UIC0>;
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interrupts = <3 4>;
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};
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EMAC0: ethernet@10000800 {
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linux,network-index = <0>;
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device_type = "network";
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compatible = "ibm,emac-440spe", "ibm,emac4";
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interrupt-parent = <&UIC1>;
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interrupts = <1c 4 1d 4>;
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reg = <10000800 70>;
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local-mac-address = [000000000000];
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mal-device = <&MAL0>;
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mal-tx-channel = <0>;
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mal-rx-channel = <0>;
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cell-index = <0>;
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max-frame-size = <5dc>;
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rx-fifo-size = <1000>;
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tx-fifo-size = <800>;
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phy-mode = "gmii";
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phy-map = <00000000>;
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has-inverted-stacr-oc;
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has-new-stacr-staopc;
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};
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};
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PCIX0: pci@c0ec00000 {
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "ibm,plb-pcix-440spe", "ibm,plb-pcix";
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primary;
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large-inbound-windows;
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enable-msi-hole;
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reg = <c 0ec00000 8 /* Config space access */
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0 0 0 /* no IACK cycles */
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c 0ed00000 4 /* Special cycles */
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c 0ec80000 100 /* Internal registers */
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c 0ec80100 fc>; /* Internal messaging registers */
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/* Outbound ranges, one memory and one IO,
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* later cannot be changed
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*/
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ranges = <02000000 0 80000000 0000000d 80000000 0 80000000
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01000000 0 00000000 0000000c 08000000 0 00010000>;
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/* Inbound 2GB range starting at 0 */
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dma-ranges = <42000000 0 0 0 0 0 80000000>;
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/* This drives busses 0 to 0xf */
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bus-range = <0 f>;
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/*
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* On Katmai, the following PCI-X interrupts signals
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* have to be enabled via jumpers (only INTA is
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* enabled per default):
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*
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* INTB: J3: 1-2
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* INTC: J2: 1-2
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* INTD: J1: 1-2
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*/
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interrupt-map-mask = <f800 0 0 7>;
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interrupt-map = <
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/* IDSEL 1 */
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0800 0 0 1 &UIC1 14 8
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0800 0 0 2 &UIC1 13 8
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0800 0 0 3 &UIC1 12 8
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0800 0 0 4 &UIC1 11 8
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>;
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};
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PCIE0: pciex@d00000000 {
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
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primary;
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port = <0>; /* port number */
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reg = <d 00000000 20000000 /* Config space access */
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c 10000000 00001000>; /* Registers */
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dcr-reg = <100 020>;
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sdr-base = <300>;
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/* Outbound ranges, one memory and one IO,
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* later cannot be changed
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*/
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ranges = <02000000 0 80000000 0000000e 00000000 0 80000000
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01000000 0 00000000 0000000f 80000000 0 00010000>;
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/* Inbound 2GB range starting at 0 */
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dma-ranges = <42000000 0 0 0 0 0 80000000>;
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/* This drives busses 10 to 0x1f */
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bus-range = <10 1f>;
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/* Legacy interrupts (note the weird polarity, the bridge seems
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* to invert PCIe legacy interrupts).
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* We are de-swizzling here because the numbers are actually for
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* port of the root complex virtual P2P bridge. But I want
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* to avoid putting a node for it in the tree, so the numbers
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* below are basically de-swizzled numbers.
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* The real slot is on idsel 0, so the swizzling is 1:1
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*/
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interrupt-map-mask = <0000 0 0 7>;
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interrupt-map = <
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0000 0 0 1 &UIC3 0 4 /* swizzled int A */
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0000 0 0 2 &UIC3 1 4 /* swizzled int B */
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0000 0 0 3 &UIC3 2 4 /* swizzled int C */
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0000 0 0 4 &UIC3 3 4 /* swizzled int D */>;
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};
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PCIE1: pciex@d20000000 {
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
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primary;
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port = <1>; /* port number */
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reg = <d 20000000 20000000 /* Config space access */
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c 10001000 00001000>; /* Registers */
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dcr-reg = <120 020>;
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sdr-base = <340>;
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/* Outbound ranges, one memory and one IO,
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* later cannot be changed
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*/
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ranges = <02000000 0 80000000 0000000e 80000000 0 80000000
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01000000 0 00000000 0000000f 80010000 0 00010000>;
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/* Inbound 2GB range starting at 0 */
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dma-ranges = <42000000 0 0 0 0 0 80000000>;
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/* This drives busses 10 to 0x1f */
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bus-range = <20 2f>;
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/* Legacy interrupts (note the weird polarity, the bridge seems
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* to invert PCIe legacy interrupts).
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* We are de-swizzling here because the numbers are actually for
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* port of the root complex virtual P2P bridge. But I want
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* to avoid putting a node for it in the tree, so the numbers
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* below are basically de-swizzled numbers.
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* The real slot is on idsel 0, so the swizzling is 1:1
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*/
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interrupt-map-mask = <0000 0 0 7>;
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interrupt-map = <
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0000 0 0 1 &UIC3 4 4 /* swizzled int A */
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0000 0 0 2 &UIC3 5 4 /* swizzled int B */
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0000 0 0 3 &UIC3 6 4 /* swizzled int C */
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0000 0 0 4 &UIC3 7 4 /* swizzled int D */>;
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};
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PCIE2: pciex@d40000000 {
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device_type = "pci";
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#interrupt-cells = <1>;
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#size-cells = <2>;
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#address-cells = <3>;
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compatible = "ibm,plb-pciex-440spe", "ibm,plb-pciex";
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primary;
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port = <2>; /* port number */
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reg = <d 40000000 20000000 /* Config space access */
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c 10002000 00001000>; /* Registers */
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dcr-reg = <140 020>;
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sdr-base = <370>;
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/* Outbound ranges, one memory and one IO,
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* later cannot be changed
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*/
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ranges = <02000000 0 80000000 0000000f 00000000 0 80000000
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01000000 0 00000000 0000000f 80020000 0 00010000>;
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/* Inbound 2GB range starting at 0 */
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dma-ranges = <42000000 0 0 0 0 0 80000000>;
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/* This drives busses 10 to 0x1f */
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bus-range = <30 3f>;
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/* Legacy interrupts (note the weird polarity, the bridge seems
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* to invert PCIe legacy interrupts).
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* We are de-swizzling here because the numbers are actually for
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* port of the root complex virtual P2P bridge. But I want
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* to avoid putting a node for it in the tree, so the numbers
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* below are basically de-swizzled numbers.
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* The real slot is on idsel 0, so the swizzling is 1:1
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*/
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interrupt-map-mask = <0000 0 0 7>;
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interrupt-map = <
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0000 0 0 1 &UIC3 8 4 /* swizzled int A */
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0000 0 0 2 &UIC3 9 4 /* swizzled int B */
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0000 0 0 3 &UIC3 a 4 /* swizzled int C */
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0000 0 0 4 &UIC3 b 4 /* swizzled int D */>;
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};
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};
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chosen {
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linux,stdout-path = "/plb/opb/serial@10000200";
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};
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};
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