0b9afede3d
Machine vector selection has always been a bit of a hack given how early in system boot it needs to be done. Services like ACPI namespace are not available and there are non-trivial problems to moving them to early boot. However, there's no reason we can't change to a different machvec later in boot when the services we need are available. By adding a entry point for later initialization of the swiotlb, we can add an error path for the hpzx1 machevec initialization and fall back to the DIG machine vector if IOMMU hardware isn't found in the system. Since ia64 uses 4GB for zone DMA (no ISA support), it's trivial to allocate a contiguous range from the slab for bounce buffer usage. Signed-off-by: Alex Williamson <alex.williamson@hp.com> Signed-off-by: Tony Luck <tony.luck@intel.com>
195 lines
5.7 KiB
C
195 lines
5.7 KiB
C
/*
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* Copyright (c) 2004 Hewlett-Packard Development Company, L.P.
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* Contributed by David Mosberger-Tang <davidm@hpl.hp.com>
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*
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* This is a pseudo I/O MMU which dispatches to the hardware I/O MMU
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* whenever possible. We assume that the hardware I/O MMU requires
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* full 32-bit addressability, as is the case, e.g., for HP zx1-based
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* systems (there, the I/O MMU window is mapped at 3-4GB). If a
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* device doesn't provide full 32-bit addressability, we fall back on
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* the sw I/O TLB. This is good enough to let us support broken
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* hardware such as soundcards which have a DMA engine that can
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* address only 28 bits.
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*/
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#include <linux/device.h>
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#include <asm/machvec.h>
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/* swiotlb declarations & definitions: */
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extern int swiotlb_late_init_with_default_size (size_t size);
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extern ia64_mv_dma_alloc_coherent swiotlb_alloc_coherent;
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extern ia64_mv_dma_free_coherent swiotlb_free_coherent;
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extern ia64_mv_dma_map_single swiotlb_map_single;
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extern ia64_mv_dma_unmap_single swiotlb_unmap_single;
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extern ia64_mv_dma_map_sg swiotlb_map_sg;
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extern ia64_mv_dma_unmap_sg swiotlb_unmap_sg;
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extern ia64_mv_dma_supported swiotlb_dma_supported;
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extern ia64_mv_dma_mapping_error swiotlb_dma_mapping_error;
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/* hwiommu declarations & definitions: */
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extern ia64_mv_dma_alloc_coherent sba_alloc_coherent;
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extern ia64_mv_dma_free_coherent sba_free_coherent;
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extern ia64_mv_dma_map_single sba_map_single;
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extern ia64_mv_dma_unmap_single sba_unmap_single;
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extern ia64_mv_dma_map_sg sba_map_sg;
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extern ia64_mv_dma_unmap_sg sba_unmap_sg;
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extern ia64_mv_dma_supported sba_dma_supported;
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extern ia64_mv_dma_mapping_error sba_dma_mapping_error;
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#define hwiommu_alloc_coherent sba_alloc_coherent
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#define hwiommu_free_coherent sba_free_coherent
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#define hwiommu_map_single sba_map_single
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#define hwiommu_unmap_single sba_unmap_single
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#define hwiommu_map_sg sba_map_sg
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#define hwiommu_unmap_sg sba_unmap_sg
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#define hwiommu_dma_supported sba_dma_supported
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#define hwiommu_dma_mapping_error sba_dma_mapping_error
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#define hwiommu_sync_single_for_cpu machvec_dma_sync_single
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#define hwiommu_sync_sg_for_cpu machvec_dma_sync_sg
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#define hwiommu_sync_single_for_device machvec_dma_sync_single
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#define hwiommu_sync_sg_for_device machvec_dma_sync_sg
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/*
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* Note: we need to make the determination of whether or not to use
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* the sw I/O TLB based purely on the device structure. Anything else
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* would be unreliable or would be too intrusive.
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*/
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static inline int
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use_swiotlb (struct device *dev)
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{
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return dev && dev->dma_mask && !hwiommu_dma_supported(dev, *dev->dma_mask);
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}
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void
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hwsw_init (void)
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{
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/* default to a smallish 2MB sw I/O TLB */
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if (swiotlb_late_init_with_default_size (2 * (1<<20)) != 0) {
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#ifdef CONFIG_IA64_GENERIC
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/* Better to have normal DMA than panic */
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printk(KERN_WARNING "%s: Failed to initialize software I/O TLB,"
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" reverting to hpzx1 platform vector\n", __FUNCTION__);
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machvec_init("hpzx1");
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#else
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panic("Unable to initialize software I/O TLB services");
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#endif
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}
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}
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void *
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hwsw_alloc_coherent (struct device *dev, size_t size, dma_addr_t *dma_handle, int flags)
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{
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if (use_swiotlb(dev))
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return swiotlb_alloc_coherent(dev, size, dma_handle, flags);
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else
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return hwiommu_alloc_coherent(dev, size, dma_handle, flags);
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}
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void
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hwsw_free_coherent (struct device *dev, size_t size, void *vaddr, dma_addr_t dma_handle)
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{
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if (use_swiotlb(dev))
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swiotlb_free_coherent(dev, size, vaddr, dma_handle);
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else
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hwiommu_free_coherent(dev, size, vaddr, dma_handle);
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}
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dma_addr_t
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hwsw_map_single (struct device *dev, void *addr, size_t size, int dir)
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{
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if (use_swiotlb(dev))
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return swiotlb_map_single(dev, addr, size, dir);
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else
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return hwiommu_map_single(dev, addr, size, dir);
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}
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void
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hwsw_unmap_single (struct device *dev, dma_addr_t iova, size_t size, int dir)
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{
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if (use_swiotlb(dev))
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return swiotlb_unmap_single(dev, iova, size, dir);
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else
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return hwiommu_unmap_single(dev, iova, size, dir);
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}
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int
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hwsw_map_sg (struct device *dev, struct scatterlist *sglist, int nents, int dir)
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{
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if (use_swiotlb(dev))
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return swiotlb_map_sg(dev, sglist, nents, dir);
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else
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return hwiommu_map_sg(dev, sglist, nents, dir);
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}
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void
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hwsw_unmap_sg (struct device *dev, struct scatterlist *sglist, int nents, int dir)
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{
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if (use_swiotlb(dev))
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return swiotlb_unmap_sg(dev, sglist, nents, dir);
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else
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return hwiommu_unmap_sg(dev, sglist, nents, dir);
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}
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void
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hwsw_sync_single_for_cpu (struct device *dev, dma_addr_t addr, size_t size, int dir)
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{
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if (use_swiotlb(dev))
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swiotlb_sync_single_for_cpu(dev, addr, size, dir);
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else
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hwiommu_sync_single_for_cpu(dev, addr, size, dir);
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}
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void
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hwsw_sync_sg_for_cpu (struct device *dev, struct scatterlist *sg, int nelems, int dir)
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{
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if (use_swiotlb(dev))
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swiotlb_sync_sg_for_cpu(dev, sg, nelems, dir);
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else
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hwiommu_sync_sg_for_cpu(dev, sg, nelems, dir);
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}
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void
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hwsw_sync_single_for_device (struct device *dev, dma_addr_t addr, size_t size, int dir)
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{
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if (use_swiotlb(dev))
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swiotlb_sync_single_for_device(dev, addr, size, dir);
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else
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hwiommu_sync_single_for_device(dev, addr, size, dir);
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}
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void
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hwsw_sync_sg_for_device (struct device *dev, struct scatterlist *sg, int nelems, int dir)
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{
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if (use_swiotlb(dev))
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swiotlb_sync_sg_for_device(dev, sg, nelems, dir);
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else
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hwiommu_sync_sg_for_device(dev, sg, nelems, dir);
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}
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int
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hwsw_dma_supported (struct device *dev, u64 mask)
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{
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if (hwiommu_dma_supported(dev, mask))
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return 1;
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return swiotlb_dma_supported(dev, mask);
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}
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int
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hwsw_dma_mapping_error (dma_addr_t dma_addr)
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{
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return hwiommu_dma_mapping_error (dma_addr) || swiotlb_dma_mapping_error(dma_addr);
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}
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EXPORT_SYMBOL(hwsw_dma_mapping_error);
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EXPORT_SYMBOL(hwsw_map_single);
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EXPORT_SYMBOL(hwsw_unmap_single);
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EXPORT_SYMBOL(hwsw_map_sg);
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EXPORT_SYMBOL(hwsw_unmap_sg);
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EXPORT_SYMBOL(hwsw_dma_supported);
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EXPORT_SYMBOL(hwsw_alloc_coherent);
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EXPORT_SYMBOL(hwsw_free_coherent);
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