65316fd13a
generic__raw_read_trylock() is a defect generic function actually doing a __raw_read_lock ... Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
332 lines
7.3 KiB
C
332 lines
7.3 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1999, 2000 by Ralf Baechle
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* Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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*/
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#ifndef _ASM_SPINLOCK_H
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#define _ASM_SPINLOCK_H
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#include <asm/war.h>
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/*
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* Your basic SMP spinlocks, allowing only a single CPU anywhere
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*/
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#define __raw_spin_is_locked(x) ((x)->lock != 0)
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#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
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#define __raw_spin_unlock_wait(x) \
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do { cpu_relax(); } while ((x)->lock)
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/*
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* Simple spin lock operations. There are two variants, one clears IRQ's
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* on the local processor, one does not.
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*
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* We make no fairness assumptions. They have a cost.
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*/
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static inline void __raw_spin_lock(raw_spinlock_t *lock)
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{
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unsigned int tmp;
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if (R10000_LLSC_WAR) {
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__asm__ __volatile__(
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" .set noreorder # __raw_spin_lock \n"
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"1: ll %1, %2 \n"
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" bnez %1, 1b \n"
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" li %1, 1 \n"
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" sc %1, %0 \n"
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" beqzl %1, 1b \n"
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" nop \n"
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" sync \n"
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" .set reorder \n"
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: "=m" (lock->lock), "=&r" (tmp)
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: "m" (lock->lock)
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: "memory");
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} else {
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__asm__ __volatile__(
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" .set noreorder # __raw_spin_lock \n"
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"1: ll %1, %2 \n"
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" bnez %1, 1b \n"
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" li %1, 1 \n"
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" sc %1, %0 \n"
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" beqz %1, 1b \n"
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" sync \n"
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" .set reorder \n"
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: "=m" (lock->lock), "=&r" (tmp)
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: "m" (lock->lock)
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: "memory");
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}
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}
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static inline void __raw_spin_unlock(raw_spinlock_t *lock)
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{
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__asm__ __volatile__(
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" .set noreorder # __raw_spin_unlock \n"
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" sync \n"
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" sw $0, %0 \n"
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" .set\treorder \n"
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: "=m" (lock->lock)
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: "m" (lock->lock)
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: "memory");
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}
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static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock)
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{
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unsigned int temp, res;
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if (R10000_LLSC_WAR) {
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__asm__ __volatile__(
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" .set noreorder # __raw_spin_trylock \n"
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"1: ll %0, %3 \n"
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" ori %2, %0, 1 \n"
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" sc %2, %1 \n"
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" beqzl %2, 1b \n"
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" nop \n"
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" andi %2, %0, 1 \n"
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" sync \n"
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" .set reorder"
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: "=&r" (temp), "=m" (lock->lock), "=&r" (res)
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: "m" (lock->lock)
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: "memory");
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} else {
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__asm__ __volatile__(
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" .set noreorder # __raw_spin_trylock \n"
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"1: ll %0, %3 \n"
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" ori %2, %0, 1 \n"
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" sc %2, %1 \n"
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" beqz %2, 1b \n"
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" andi %2, %0, 1 \n"
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" sync \n"
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" .set reorder"
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: "=&r" (temp), "=m" (lock->lock), "=&r" (res)
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: "m" (lock->lock)
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: "memory");
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}
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return res == 0;
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}
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/*
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* Read-write spinlocks, allowing multiple readers but only one writer.
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*
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* NOTE! it is quite common to have readers in interrupts but no interrupt
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* writers. For those circumstances we can "mix" irq-safe locks - any writer
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* needs to get a irq-safe write-lock, but readers can get non-irqsafe
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* read-locks.
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*/
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/*
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* read_can_lock - would read_trylock() succeed?
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* @lock: the rwlock in question.
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*/
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#define __raw_read_can_lock(rw) ((rw)->lock >= 0)
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/*
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* write_can_lock - would write_trylock() succeed?
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* @lock: the rwlock in question.
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*/
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#define __raw_write_can_lock(rw) (!(rw)->lock)
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static inline void __raw_read_lock(raw_rwlock_t *rw)
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{
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unsigned int tmp;
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if (R10000_LLSC_WAR) {
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__asm__ __volatile__(
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" .set noreorder # __raw_read_lock \n"
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"1: ll %1, %2 \n"
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" bltz %1, 1b \n"
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" addu %1, 1 \n"
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" sc %1, %0 \n"
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" beqzl %1, 1b \n"
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" nop \n"
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" sync \n"
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" .set reorder \n"
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: "=m" (rw->lock), "=&r" (tmp)
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: "m" (rw->lock)
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: "memory");
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} else {
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__asm__ __volatile__(
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" .set noreorder # __raw_read_lock \n"
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"1: ll %1, %2 \n"
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" bltz %1, 1b \n"
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" addu %1, 1 \n"
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" sc %1, %0 \n"
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" beqz %1, 1b \n"
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" sync \n"
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" .set reorder \n"
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: "=m" (rw->lock), "=&r" (tmp)
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: "m" (rw->lock)
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: "memory");
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}
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}
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/* Note the use of sub, not subu which will make the kernel die with an
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overflow exception if we ever try to unlock an rwlock that is already
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unlocked or is being held by a writer. */
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static inline void __raw_read_unlock(raw_rwlock_t *rw)
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{
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unsigned int tmp;
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if (R10000_LLSC_WAR) {
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__asm__ __volatile__(
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"1: ll %1, %2 # __raw_read_unlock \n"
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" sub %1, 1 \n"
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" sc %1, %0 \n"
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" beqzl %1, 1b \n"
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" sync \n"
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: "=m" (rw->lock), "=&r" (tmp)
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: "m" (rw->lock)
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: "memory");
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} else {
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__asm__ __volatile__(
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" .set noreorder # __raw_read_unlock \n"
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"1: ll %1, %2 \n"
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" sub %1, 1 \n"
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" sc %1, %0 \n"
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" beqz %1, 1b \n"
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" sync \n"
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" .set reorder \n"
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: "=m" (rw->lock), "=&r" (tmp)
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: "m" (rw->lock)
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: "memory");
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}
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}
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static inline void __raw_write_lock(raw_rwlock_t *rw)
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{
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unsigned int tmp;
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if (R10000_LLSC_WAR) {
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__asm__ __volatile__(
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" .set noreorder # __raw_write_lock \n"
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"1: ll %1, %2 \n"
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" bnez %1, 1b \n"
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" lui %1, 0x8000 \n"
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" sc %1, %0 \n"
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" beqzl %1, 1b \n"
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" sync \n"
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" .set reorder \n"
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: "=m" (rw->lock), "=&r" (tmp)
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: "m" (rw->lock)
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: "memory");
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} else {
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__asm__ __volatile__(
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" .set noreorder # __raw_write_lock \n"
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"1: ll %1, %2 \n"
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" bnez %1, 1b \n"
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" lui %1, 0x8000 \n"
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" sc %1, %0 \n"
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" beqz %1, 1b \n"
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" sync \n"
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" .set reorder \n"
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: "=m" (rw->lock), "=&r" (tmp)
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: "m" (rw->lock)
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: "memory");
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}
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}
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static inline void __raw_write_unlock(raw_rwlock_t *rw)
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{
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__asm__ __volatile__(
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" sync # __raw_write_unlock \n"
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" sw $0, %0 \n"
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: "=m" (rw->lock)
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: "m" (rw->lock)
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: "memory");
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}
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static inline int __raw_read_trylock(raw_rwlock_t *rw)
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{
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unsigned int tmp;
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int ret;
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if (R10000_LLSC_WAR) {
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__asm__ __volatile__(
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" .set noreorder # __raw_read_trylock \n"
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" li %2, 0 \n"
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"1: ll %1, %3 \n"
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" bnez %1, 2f \n"
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" addu %1, 1 \n"
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" sc %1, %0 \n"
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" beqzl %1, 1b \n"
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" .set reorder \n"
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#ifdef CONFIG_SMP
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" sync \n"
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#endif
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" li %2, 1 \n"
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"2: \n"
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: "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
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: "m" (rw->lock)
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: "memory");
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} else {
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__asm__ __volatile__(
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" .set noreorder # __raw_read_trylock \n"
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" li %2, 0 \n"
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"1: ll %1, %3 \n"
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" bnez %1, 2f \n"
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" addu %1, 1 \n"
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" sc %1, %0 \n"
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" beqz %1, 1b \n"
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" .set reorder \n"
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#ifdef CONFIG_SMP
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" sync \n"
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#endif
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" li %2, 1 \n"
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"2: \n"
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: "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
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: "m" (rw->lock)
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: "memory");
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}
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return ret;
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}
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static inline int __raw_write_trylock(raw_rwlock_t *rw)
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{
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unsigned int tmp;
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int ret;
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if (R10000_LLSC_WAR) {
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__asm__ __volatile__(
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" .set noreorder # __raw_write_trylock \n"
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" li %2, 0 \n"
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"1: ll %1, %3 \n"
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" bnez %1, 2f \n"
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" lui %1, 0x8000 \n"
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" sc %1, %0 \n"
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" beqzl %1, 1b \n"
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" sync \n"
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" li %2, 1 \n"
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" .set reorder \n"
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"2: \n"
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: "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
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: "m" (rw->lock)
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: "memory");
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} else {
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__asm__ __volatile__(
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" .set noreorder # __raw_write_trylock \n"
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" li %2, 0 \n"
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"1: ll %1, %3 \n"
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" bnez %1, 2f \n"
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" lui %1, 0x8000 \n"
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" sc %1, %0 \n"
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" beqz %1, 1b \n"
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" sync \n"
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" li %2, 1 \n"
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" .set reorder \n"
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"2: \n"
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: "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
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: "m" (rw->lock)
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: "memory");
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}
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return ret;
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}
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#endif /* _ASM_SPINLOCK_H */
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