fd84f0ee50
This patch modifies the bitbanged MDIO driver in the ep8248e platform code to use the common of_mdio infrastructure. Signed-off-by: Grant Likely <grant.likely@secretlab.ca> Acked-by: Andy Fleming <afleming@freescale.com> Signed-off-by: David S. Miller <davem@davemloft.net>
322 lines
8.3 KiB
C
322 lines
8.3 KiB
C
/*
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* Embedded Planet EP8248E support
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*
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* Copyright 2007 Freescale Semiconductor, Inc.
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* Author: Scott Wood <scottwood@freescale.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/fsl_devices.h>
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#include <linux/mdio-bitbang.h>
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#include <linux/of_mdio.h>
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#include <linux/of_platform.h>
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#include <asm/io.h>
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#include <asm/cpm2.h>
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#include <asm/udbg.h>
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#include <asm/machdep.h>
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#include <asm/time.h>
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#include <asm/mpc8260.h>
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#include <asm/prom.h>
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#include <sysdev/fsl_soc.h>
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#include <sysdev/cpm2_pic.h>
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#include "pq2.h"
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static u8 __iomem *ep8248e_bcsr;
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static struct device_node *ep8248e_bcsr_node;
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#define BCSR7_SCC2_ENABLE 0x10
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#define BCSR8_PHY1_ENABLE 0x80
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#define BCSR8_PHY1_POWER 0x40
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#define BCSR8_PHY2_ENABLE 0x20
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#define BCSR8_PHY2_POWER 0x10
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#define BCSR8_MDIO_READ 0x04
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#define BCSR8_MDIO_CLOCK 0x02
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#define BCSR8_MDIO_DATA 0x01
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#define BCSR9_USB_ENABLE 0x80
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#define BCSR9_USB_POWER 0x40
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#define BCSR9_USB_HOST 0x20
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#define BCSR9_USB_FULL_SPEED_TARGET 0x10
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static void __init ep8248e_pic_init(void)
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{
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struct device_node *np = of_find_compatible_node(NULL, NULL, "fsl,pq2-pic");
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if (!np) {
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printk(KERN_ERR "PIC init: can not find cpm-pic node\n");
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return;
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}
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cpm2_pic_init(np);
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of_node_put(np);
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}
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static void ep8248e_set_mdc(struct mdiobb_ctrl *ctrl, int level)
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{
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if (level)
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setbits8(&ep8248e_bcsr[8], BCSR8_MDIO_CLOCK);
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else
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clrbits8(&ep8248e_bcsr[8], BCSR8_MDIO_CLOCK);
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/* Read back to flush the write. */
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in_8(&ep8248e_bcsr[8]);
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}
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static void ep8248e_set_mdio_dir(struct mdiobb_ctrl *ctrl, int output)
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{
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if (output)
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clrbits8(&ep8248e_bcsr[8], BCSR8_MDIO_READ);
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else
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setbits8(&ep8248e_bcsr[8], BCSR8_MDIO_READ);
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/* Read back to flush the write. */
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in_8(&ep8248e_bcsr[8]);
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}
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static void ep8248e_set_mdio_data(struct mdiobb_ctrl *ctrl, int data)
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{
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if (data)
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setbits8(&ep8248e_bcsr[8], BCSR8_MDIO_DATA);
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else
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clrbits8(&ep8248e_bcsr[8], BCSR8_MDIO_DATA);
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/* Read back to flush the write. */
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in_8(&ep8248e_bcsr[8]);
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}
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static int ep8248e_get_mdio_data(struct mdiobb_ctrl *ctrl)
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{
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return in_8(&ep8248e_bcsr[8]) & BCSR8_MDIO_DATA;
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}
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static const struct mdiobb_ops ep8248e_mdio_ops = {
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.set_mdc = ep8248e_set_mdc,
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.set_mdio_dir = ep8248e_set_mdio_dir,
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.set_mdio_data = ep8248e_set_mdio_data,
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.get_mdio_data = ep8248e_get_mdio_data,
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.owner = THIS_MODULE,
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};
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static struct mdiobb_ctrl ep8248e_mdio_ctrl = {
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.ops = &ep8248e_mdio_ops,
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};
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static int __devinit ep8248e_mdio_probe(struct of_device *ofdev,
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const struct of_device_id *match)
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{
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struct mii_bus *bus;
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struct resource res;
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struct device_node *node;
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int ret;
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node = of_get_parent(ofdev->node);
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of_node_put(node);
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if (node != ep8248e_bcsr_node)
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return -ENODEV;
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ret = of_address_to_resource(ofdev->node, 0, &res);
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if (ret)
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return ret;
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bus = alloc_mdio_bitbang(&ep8248e_mdio_ctrl);
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if (!bus)
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return -ENOMEM;
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bus->irq = kmalloc(sizeof(int) * PHY_MAX_ADDR, GFP_KERNEL);
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bus->name = "ep8248e-mdio-bitbang";
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bus->parent = &ofdev->dev;
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snprintf(bus->id, MII_BUS_ID_SIZE, "%x", res.start);
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return of_mdiobus_register(bus, ofdev->node);
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}
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static int ep8248e_mdio_remove(struct of_device *ofdev)
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{
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BUG();
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return 0;
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}
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static const struct of_device_id ep8248e_mdio_match[] = {
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{
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.compatible = "fsl,ep8248e-mdio-bitbang",
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},
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{},
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};
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static struct of_platform_driver ep8248e_mdio_driver = {
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.driver = {
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.name = "ep8248e-mdio-bitbang",
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},
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.match_table = ep8248e_mdio_match,
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.probe = ep8248e_mdio_probe,
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.remove = ep8248e_mdio_remove,
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};
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struct cpm_pin {
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int port, pin, flags;
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};
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static __initdata struct cpm_pin ep8248e_pins[] = {
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/* SMC1 */
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{2, 4, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{2, 5, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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/* SCC1 */
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{2, 14, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{2, 15, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{3, 29, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{3, 30, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
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{3, 31, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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/* FCC1 */
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{0, 14, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{0, 15, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{0, 16, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{0, 17, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{0, 18, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{0, 19, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{0, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{0, 21, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{0, 26, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
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{0, 27, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
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{0, 28, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
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{0, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
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{0, 30, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
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{0, 31, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
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{2, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{2, 22, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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/* FCC2 */
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{1, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 20, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 21, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 22, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{1, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{1, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{1, 25, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{1, 26, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 27, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 28, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 29, CPM_PIN_OUTPUT | CPM_PIN_SECONDARY},
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{1, 30, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{1, 31, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{2, 18, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{2, 19, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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/* I2C */
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{4, 14, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
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{4, 15, CPM_PIN_INPUT | CPM_PIN_SECONDARY},
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/* USB */
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{2, 10, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{2, 11, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{2, 20, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{2, 24, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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{3, 23, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{3, 24, CPM_PIN_OUTPUT | CPM_PIN_PRIMARY},
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{3, 25, CPM_PIN_INPUT | CPM_PIN_PRIMARY},
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};
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static void __init init_ioports(void)
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{
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int i;
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for (i = 0; i < ARRAY_SIZE(ep8248e_pins); i++) {
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const struct cpm_pin *pin = &ep8248e_pins[i];
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cpm2_set_pin(pin->port, pin->pin, pin->flags);
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}
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cpm2_smc_clk_setup(CPM_CLK_SMC1, CPM_BRG7);
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cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_RX);
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cpm2_clk_setup(CPM_CLK_SCC1, CPM_BRG1, CPM_CLK_TX);
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cpm2_clk_setup(CPM_CLK_SCC3, CPM_CLK8, CPM_CLK_TX); /* USB */
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cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK11, CPM_CLK_RX);
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cpm2_clk_setup(CPM_CLK_FCC1, CPM_CLK10, CPM_CLK_TX);
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cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK13, CPM_CLK_RX);
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cpm2_clk_setup(CPM_CLK_FCC2, CPM_CLK14, CPM_CLK_TX);
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}
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static void __init ep8248e_setup_arch(void)
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{
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if (ppc_md.progress)
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ppc_md.progress("ep8248e_setup_arch()", 0);
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cpm2_reset();
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/* When this is set, snooping CPM DMA from RAM causes
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* machine checks. See erratum SIU18.
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*/
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clrbits32(&cpm2_immr->im_siu_conf.siu_82xx.sc_bcr, MPC82XX_BCR_PLDP);
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ep8248e_bcsr_node =
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of_find_compatible_node(NULL, NULL, "fsl,ep8248e-bcsr");
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if (!ep8248e_bcsr_node) {
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printk(KERN_ERR "No bcsr in device tree\n");
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return;
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}
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ep8248e_bcsr = of_iomap(ep8248e_bcsr_node, 0);
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if (!ep8248e_bcsr) {
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printk(KERN_ERR "Cannot map BCSR registers\n");
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of_node_put(ep8248e_bcsr_node);
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ep8248e_bcsr_node = NULL;
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return;
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}
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setbits8(&ep8248e_bcsr[7], BCSR7_SCC2_ENABLE);
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setbits8(&ep8248e_bcsr[8], BCSR8_PHY1_ENABLE | BCSR8_PHY1_POWER |
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BCSR8_PHY2_ENABLE | BCSR8_PHY2_POWER);
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init_ioports();
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if (ppc_md.progress)
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ppc_md.progress("ep8248e_setup_arch(), finish", 0);
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}
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static __initdata struct of_device_id of_bus_ids[] = {
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{ .compatible = "simple-bus", },
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{ .compatible = "fsl,ep8248e-bcsr", },
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{},
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};
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static int __init declare_of_platform_devices(void)
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{
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of_platform_bus_probe(NULL, of_bus_ids, NULL);
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of_register_platform_driver(&ep8248e_mdio_driver);
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return 0;
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}
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machine_device_initcall(ep8248e, declare_of_platform_devices);
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/*
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* Called very early, device-tree isn't unflattened
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*/
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static int __init ep8248e_probe(void)
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{
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unsigned long root = of_get_flat_dt_root();
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return of_flat_dt_is_compatible(root, "fsl,ep8248e");
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}
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define_machine(ep8248e)
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{
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.name = "Embedded Planet EP8248E",
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.probe = ep8248e_probe,
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.setup_arch = ep8248e_setup_arch,
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.init_IRQ = ep8248e_pic_init,
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.get_irq = cpm2_get_irq,
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.calibrate_decr = generic_calibrate_decr,
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.restart = pq2_restart,
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.progress = udbg_progress,
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};
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