0e037bbb4a
Signed-off-by: eric miao <eric.miao@marvell.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
168 lines
3.7 KiB
C
168 lines
3.7 KiB
C
/*
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* linux/arch/arm/mach-pxa/gpio.c
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*
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* Generic PXA GPIO handling
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*
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* Author: Nicolas Pitre
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* Created: Jun 15, 2001
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* Copyright: MontaVista Software Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <asm/gpio.h>
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#include <asm/hardware.h>
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#include <asm/io.h>
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#include <asm/arch/pxa-regs.h>
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#include "generic.h"
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struct pxa_gpio_chip {
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struct gpio_chip chip;
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void __iomem *regbase;
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};
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int pxa_last_gpio;
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/*
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* Configure pins for GPIO or other functions
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*/
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int pxa_gpio_mode(int gpio_mode)
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{
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unsigned long flags;
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int gpio = gpio_mode & GPIO_MD_MASK_NR;
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int fn = (gpio_mode & GPIO_MD_MASK_FN) >> 8;
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int gafr;
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if (gpio > pxa_last_gpio)
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return -EINVAL;
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local_irq_save(flags);
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if (gpio_mode & GPIO_DFLT_LOW)
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GPCR(gpio) = GPIO_bit(gpio);
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else if (gpio_mode & GPIO_DFLT_HIGH)
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GPSR(gpio) = GPIO_bit(gpio);
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if (gpio_mode & GPIO_MD_MASK_DIR)
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GPDR(gpio) |= GPIO_bit(gpio);
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else
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GPDR(gpio) &= ~GPIO_bit(gpio);
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gafr = GAFR(gpio) & ~(0x3 << (((gpio) & 0xf)*2));
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GAFR(gpio) = gafr | (fn << (((gpio) & 0xf)*2));
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local_irq_restore(flags);
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return 0;
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}
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EXPORT_SYMBOL(pxa_gpio_mode);
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static int pxa_gpio_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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unsigned long flags;
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u32 mask = 1 << offset;
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u32 value;
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struct pxa_gpio_chip *pxa;
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void __iomem *gpdr;
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pxa = container_of(chip, struct pxa_gpio_chip, chip);
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gpdr = pxa->regbase + GPDR_OFFSET;
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local_irq_save(flags);
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value = __raw_readl(gpdr);
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value &= ~mask;
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__raw_writel(value, gpdr);
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local_irq_restore(flags);
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return 0;
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}
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static int pxa_gpio_direction_output(struct gpio_chip *chip,
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unsigned offset, int value)
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{
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unsigned long flags;
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u32 mask = 1 << offset;
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u32 tmp;
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struct pxa_gpio_chip *pxa;
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void __iomem *gpdr;
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pxa = container_of(chip, struct pxa_gpio_chip, chip);
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__raw_writel(mask,
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pxa->regbase + (value ? GPSR_OFFSET : GPCR_OFFSET));
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gpdr = pxa->regbase + GPDR_OFFSET;
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local_irq_save(flags);
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tmp = __raw_readl(gpdr);
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tmp |= mask;
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__raw_writel(tmp, gpdr);
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local_irq_restore(flags);
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return 0;
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}
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/*
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* Return GPIO level
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*/
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static int pxa_gpio_get(struct gpio_chip *chip, unsigned offset)
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{
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u32 mask = 1 << offset;
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struct pxa_gpio_chip *pxa;
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pxa = container_of(chip, struct pxa_gpio_chip, chip);
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return __raw_readl(pxa->regbase + GPLR_OFFSET) & mask;
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}
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/*
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* Set output GPIO level
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*/
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static void pxa_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
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{
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u32 mask = 1 << offset;
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struct pxa_gpio_chip *pxa;
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pxa = container_of(chip, struct pxa_gpio_chip, chip);
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if (value)
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__raw_writel(mask, pxa->regbase + GPSR_OFFSET);
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else
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__raw_writel(mask, pxa->regbase + GPCR_OFFSET);
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}
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#define GPIO_CHIP(_n) \
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[_n] = { \
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.regbase = GPIO##_n##_BASE, \
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.chip = { \
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.label = "gpio-" #_n, \
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.direction_input = pxa_gpio_direction_input, \
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.direction_output = pxa_gpio_direction_output, \
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.get = pxa_gpio_get, \
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.set = pxa_gpio_set, \
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.base = (_n) * 32, \
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.ngpio = 32, \
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}, \
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}
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static struct pxa_gpio_chip pxa_gpio_chip[] = {
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GPIO_CHIP(0),
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GPIO_CHIP(1),
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GPIO_CHIP(2),
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#if defined(CONFIG_PXA27x) || defined(CONFIG_PXA3xx)
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GPIO_CHIP(3),
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#endif
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};
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void __init pxa_init_gpio(int gpio_nr)
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{
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int i;
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/* add a GPIO chip for each register bank.
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* the last PXA25x register only contains 21 GPIOs
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*/
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for (i = 0; i < gpio_nr; i += 32) {
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if (i+32 > gpio_nr)
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pxa_gpio_chip[i/32].chip.ngpio = gpio_nr - i;
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gpiochip_add(&pxa_gpio_chip[i/32].chip);
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}
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}
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