7f1b358a23
This patch adds to ioatdma and dca modules support for Intel I/OAT DMA engine ver.3 (aka CB3 device). The main features of I/OAT ver.3 are: * 8 single channel DMA devices (8 channels total) * 8 DCA providers, each can accept 2 requesters * 8-bit TAG values and 32-bit extended APIC IDs Signed-off-by: Maciej Sosnowski <maciej.sosnowski@intel.com> Signed-off-by: Dan Williams <dan.j.williams@intel.com>
71 lines
2.4 KiB
C
71 lines
2.4 KiB
C
/*
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* Copyright(c) 2004 - 2007 Intel Corporation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the Free
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* Software Foundation; either version 2 of the License, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59
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* Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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*
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* The full GNU General Public License is included in this distribution in the
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* file called COPYING.
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*/
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#ifndef _IOAT_HW_H_
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#define _IOAT_HW_H_
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/* PCI Configuration Space Values */
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#define IOAT_PCI_VID 0x8086
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/* CB device ID's */
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#define IOAT_PCI_DID_5000 0x1A38
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#define IOAT_PCI_DID_CNB 0x360B
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#define IOAT_PCI_DID_SCNB 0x65FF
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#define IOAT_PCI_DID_SNB 0x402F
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#define IOAT_PCI_RID 0x00
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#define IOAT_PCI_SVID 0x8086
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#define IOAT_PCI_SID 0x8086
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#define IOAT_VER_1_2 0x12 /* Version 1.2 */
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#define IOAT_VER_2_0 0x20 /* Version 2.0 */
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#define IOAT_VER_3_0 0x30 /* Version 3.0 */
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struct ioat_dma_descriptor {
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uint32_t size;
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uint32_t ctl;
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uint64_t src_addr;
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uint64_t dst_addr;
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uint64_t next;
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uint64_t rsv1;
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uint64_t rsv2;
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uint64_t user1;
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uint64_t user2;
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};
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#define IOAT_DMA_DESCRIPTOR_CTL_INT_GN 0x00000001
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#define IOAT_DMA_DESCRIPTOR_CTL_SRC_SN 0x00000002
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#define IOAT_DMA_DESCRIPTOR_CTL_DST_SN 0x00000004
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#define IOAT_DMA_DESCRIPTOR_CTL_CP_STS 0x00000008
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#define IOAT_DMA_DESCRIPTOR_CTL_FRAME 0x00000010
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#define IOAT_DMA_DESCRIPTOR_NUL 0x00000020
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#define IOAT_DMA_DESCRIPTOR_CTL_SP_BRK 0x00000040
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#define IOAT_DMA_DESCRIPTOR_CTL_DP_BRK 0x00000080
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#define IOAT_DMA_DESCRIPTOR_CTL_BNDL 0x00000100
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#define IOAT_DMA_DESCRIPTOR_CTL_DCA 0x00000200
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#define IOAT_DMA_DESCRIPTOR_CTL_BUFHINT 0x00000400
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#define IOAT_DMA_DESCRIPTOR_CTL_OPCODE_CONTEXT 0xFF000000
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#define IOAT_DMA_DESCRIPTOR_CTL_OPCODE_DMA 0x00000000
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#define IOAT_DMA_DESCRIPTOR_CTL_CONTEXT_DCA 0x00000001
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#define IOAT_DMA_DESCRIPTOR_CTL_OPCODE_MASK 0xFF000000
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#endif
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