ed2b03ed3c
The way the code is written it was assuming dshd has the function of a hypothetical dshw instruction ... Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
68 lines
1.2 KiB
C
68 lines
1.2 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1996, 99, 2003 by Ralf Baechle
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*/
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#ifndef _ASM_BYTEORDER_H
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#define _ASM_BYTEORDER_H
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#include <linux/compiler.h>
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#include <asm/types.h>
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#if defined(__MIPSEB__)
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# define __BIG_ENDIAN
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#elif defined(__MIPSEL__)
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# define __LITTLE_ENDIAN
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#else
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# error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
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#endif
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#define __SWAB_64_THRU_32__
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#ifdef CONFIG_CPU_MIPSR2
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static inline __attribute_const__ __u16 __arch_swab16(__u16 x)
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{
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__asm__(
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" wsbh %0, %1 \n"
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: "=r" (x)
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: "r" (x));
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return x;
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}
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#define __arch_swab16 __arch_swab16
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static inline __attribute_const__ __u32 __arch_swab32(__u32 x)
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{
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__asm__(
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" wsbh %0, %1 \n"
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" rotr %0, %0, 16 \n"
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: "=r" (x)
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: "r" (x));
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return x;
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}
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#define __arch_swab32 __arch_swab32
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#ifdef CONFIG_CPU_MIPS64_R2
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static inline __attribute_const__ __u64 __arch_swab64(__u64 x)
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{
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__asm__(
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" dsbh %0, %1\n"
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" dshd %0, %0"
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: "=r" (x)
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: "r" (x));
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return x;
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}
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#define __arch_swab64 __arch_swab64
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#endif /* CONFIG_CPU_MIPS64_R2 */
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#endif /* CONFIG_CPU_MIPSR2 */
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#include <linux/byteorder.h>
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#endif /* _ASM_BYTEORDER_H */
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